Integrated Devices, Electronics and Systems (IDEAS) Group

We are super excited to start a new 4-year collaborative project funded by Swiss National Science Foundation SNSF MOSIAC: Multimodal Optogenetic Subcellular Neural Interfacing Array on CMOS with Multi-Color Micro-OLEDs. https://lnkd.in/eAiGdtPX The project is led by the PI Prof. Hua Wang (ETH D-ITET) and two co-PIs Prof. Chih-Jen Shih (ETH D-CHAB) and Prof. Martin Müller (UZH, Department of Molecular Life Sciences). The MOSIAC project will address several key challenges in neuronal stimulation and recording technologies by achieving the world’s first co-integration of micro-LED array and multi-modal MEA array on the same CMOS chip. It will enable cell-type-specific optogenetics and real-time multi-modal neural sensing, localization and feedback, all at an unprecedented spatio-temporal resolution to capture single neuron activities far beyond the state-of-the-art neuron interface technologies. The MOSIAC project will use the bioelectronics/nano-devices research infrastructure of ETH Zurich, neurobiology research facilities at UZH, and the ETH FIRST cleanroom as well as the IBM Zurich BRNC cleanroom. We envision that the MOSIAC project will pave the way for new medical advancements, clinical treatments, and drug development. On the societal impact, the MOSIAC project will foster bioelectronics and neuroscience collaborations in Swiss academia and worldwide. It will further enhance Switzerland’s core competence on semiconductors, neuroscience, medicine, and healthcare.

We are delighted to announce that our PhD student, Jinglong Xu, has won the Young Engineer Prize (GaAs Award) at the 2025 European Microwave Integrated Circuits Conference (EuMIC) in Utrecht Netherland, for his paper "An Ultra-Compact Ku-Band Doherty Power Amplifier with a Single-Footprint Triple Two-Turn Asymmetric Doherty Combiner for 6G FR3". Congratulating on this remarkable achievement, Jinglong! #EuMIC #EuMW

We are delighted to welcome Professor Thomas Cho from KAIST as a guest of our IDEAS Group. Prof. Cho brings a unique blend of academic excellence and real-world industry experience. His work has shaped the technologies we use every day, from wireless communication systems to advanced IC and RF designs, and has ranged from co-founding a startup in California to leading major engineering teams at companies like Marvell and Samsung Electronics. During his visit, he will meet with our group members and share his insights. We are thrilled to have him with us. Welcome to ETH Zurich, Prof. Cho! https://lnkd.in/djqx3nPg

We just posted the tenth version of our PA Survey. This version 10 dataset includes PAs/transmitters from 500MHz to 1.5 THz in Bulk/SOI CMOS, SiGe, LDMOS, InP, GaN, GaAs technologies. The dataset contains total 5073 data points with 1751 data points for CMOS, SiGe PAs and 3066 data points for GaN, GaAs, InP, and LDMOS PAs as well data points from other technologies. https://lnkd.in/emgA92rk We also made the third release of our LNA survey. This survey collects the published silicon/SiGe low noise amplifier (LNAs) noise figure from 2018 to present, focusing on LNAs with carrier frequencies from 500 MHz to 300 GHz and LNAs implemented in commercially available technologies including bulk CMOS, CMOS SOI, SiGe/SiGe BiCMOS, and FinFET technologies. https://lnkd.in/eDeiZg6c ETH Zürich, ETH Zurich, Department of Information Technology and Electrical Engineering

Dr. Chenhao Chu, a postdoctoral scholar at the ETH IDEAS Group, recently presented our work on AI-Assisted Template-Seeded Pixelated Design for Multi-Metal-Layer High-Coupling Electromagnetic Structures, and its application in a Ku-Band 6G FR3 Power Amplifier using GlobalFoundries 22nm FDX+ technology. This "Template-Seeded Pixelated Approach" offers an effective and adjustable balance between exploring new topologies and managing the complexity of data generation. Our group began investigating AI-assisted RFIC design with our early efforts presented at RFIC 2020 (https://lnkd.in/e-weKz3V) and IMS 2021 (https://lnkd.in/eF_JP9uc). It is truly remarkable to witness the rapid progress of this field over the past five years. We are deeply grateful to our government sponsors and industry collaborators, especially SwissChips, Mitsubishi Electric, and GlobalFoundries, for their continued support. Chenhao Chu, Torii, Shintaro Shinjo, Koji Yamanaka, Jinglong Xu, Yuqi Liu, Jianping Zeng, Adam Wang ETH Zürich, ETH Zurich, Department of Information Technology and Electrical Engineering, SwissChips, #CHIPS, #EU, #Semiconductor

Congratulations to Edward Liu and Boce Lin on passing their PhD exams yesterday! Edward’s thesis, "Advanced Power Amplifier Architectures in Silicon for Wireless Communications", pushes the boundaries of efficient, high-performance RF design in silicon, which is critical for the next generation of wireless systems. Boce’s thesis, "Design and Optimization of Novel mm-Wave Receiver Architecture for High-Performance Wireless Communication," opens new frontiers in mm-Wave technology by addressing key challenges in modern communication systems with innovative receiver architectures. Many thanks to the thesis committees: Prof. Dr. Morteza Aramesh (ETH Zurich), Prof. Dr. Shimeng Yu (Georgia Tech), Lukas Novotny (ETH Zurich), Thomas Burger (ETH Zurich), Prof. Dr. Hans-Andrea Loeliger (ETH Zurich), Prof. Dr. Thomas Cho (KAIST), and Prof. Dr. Christoph Studer (ETH Zurich), Hua Wang (ETH Zurich) Please join us in celebrating Edward and Boce's achievements and the bright futures ahead of them!

🚀 Accelerating RFIC Design with Transfer Learning We’re excited to introduce RFIC-TL, a novel transfer learning framework developed by the ETH IDEAS Group. RFIC-TL streamlines and accelerates the design migration of mm-Wave passive components across various IC technologies, frequencies, and metal configurations. 🔍 Key Highlights: Dataset Efficiency: Models trained with RFIC-TL using only 5% of target simulation data achieve comparable or superior performance to traditional methods trained on 20% of data. This represents a notable reduction of 4X in the necessary dataset size, significantly cutting down computational overhead. Versatile Applications: Validated on a 1:1 on-chip transformer-based impedance matching network, RFIC-TL showcases adaptability and effectiveness in diverse RFIC design contexts. Open Source Commitment: Our complete PyTorch implementation is openly available on GitHub. We encourage researchers, developers, and practitioners to explore, contribute to, and utilize this framework to foster innovation and collaboration within the #AIforRFIC community. 🌐 Join our open source project: https://lnkd.in/dNBJiazr 📄 Access our paper: https://lnkd.in/dp-Ky9Fy Special thanks to our co-authors Chenhao Chu, Yuhao Mao, and Hua Wang. For more inquiries, please contact Chenhao Chu. #RFIC #DeepLearning #TransferLearning #OpenSource #ETHZurich #DITET #IDEASGroup #AIforRFIC

Today we are celebrating a major milestone for our research group - Dr Dongwon Lee has successfully defended his PhD thesis "Dynamics on CMOS Biosensor for Future Point-of-Care Devices". Congratulations, Dongwon! We wish you every success in your future endeavours. #IDEAS #ETH

Our team is excited to share that our paper, "Active and Integrated Electronic Metadevices for Future Telecommunication Circuits", led by Prof. Mohammad Samizadeh Nikoo, has been published in Nature Portfolio Communications Engineering! This study presents electronic metadevices with near-ideal linear/nonlinear operation and active three-terminal metadevices enabling parametric amplification with >50% bandwidth and data rates up to 40 Gbps, advancing future telecommunication hardware. Authors: Mohammad Samizadeh Nikoo, Chenhao Chu, Boce Lin, Yuqi Liu, Youngin Kim, Hua Wang https://lnkd.in/d_D8ieKt #Metadevices #5G #6G #IDEAS

Next week our partner "Integrated Devices, Electronics and Systems (IDEAS) Group" leaded by Pr. Dr. Hua Wang from ETH Zürich will present its work to the International Solid-State-Circuits Conference [ISSCC], taking place in San Francisco from the 16th to the 20th of February. Here are the 3 works that will be presented: 📑 Title:  5.5 An Ultra-Compact Wideband Load-Insensitive Complex-Cascode LC-Neutralized Power Amplifier for 4:1 VSWR-Resilient Operations in Large-Scale Phased-Arrays Authors: Mohamed Eleraky, and Hua Wang Session: 5. Front-End Circuits for High-Performance Transceivers Presentation: Monday, February 17th, 3:00 PM Speaker: Mohamed Eleraky 📑 Title: 10.3 A D-band 2-D Scalable 4x4 Active Reflective Relay with Orthogonally-Polarized On-Chip TX/RX Antennas and In-Frontend Common-Centroid Fast Azimuth/Elevation Angle-of-Arrival Detection Authors: Basem Abdelaziz Abdelmagid, Boce Lin and Hua Wang Session: 10. Transceiver Chipsets for Communication and Radar Presentation: Tuesday, February 18th, 8:50 AM Speaker: Basem Abdelaziz Abdelmagid 📑 Paper: 33.4 A Wideband Bi-Directional Calibration-Free Frequency/Switching-Staggering 360° D-Band Phase Shifter with Frequency-Invariant Codes Achieving < 2.38°/0.63dB RMS-Errors Over 24% Bandwidth Authors: Basem Abdelaziz Abdelmagid, Yuqi Liu and Hua Wang Session: 33. Components for Beyond 100GHz Presentation: Wednesday, February 19th, 2:45 PM Speaker: Basem Abdelaziz Abdelmagid Feel free to meet them to exchange on their work. #fdsoi #soileuproject #conference #research #presentation