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32nd MICRO 1999: Haifa, Israel

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Ronny Ronen, Matthew K. Farrens, Ilan Y. Spillinger:
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999. ACM/IEEE Computer Society 1999, ISBN 0-7695-0437-X

Welcome and Keynote

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Fred J. Pollack:
New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies. 2-

Faster FrontEnd

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Eric Rotenberg, James E. Smith:
Control Independence in Trace Processors. 4-15
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Glenn Reinman, Brad Calder, Todd M. Austin:
Fetch Directed Instruction Prefetching. 16-27
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Timothy H. Heil, Zak Smith, James E. Smith:
Improving Branch Predictors by Correlating on Data Values. 28-37
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Artur Klauser, Dirk Grunwald:
Instruction Fetch Mechanisms for Multipath Execution Processors. 38-47

3D and MultiMedia

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Andrew Wolfe, Derek B. Noonburg:
A Superscalar 3D Graphics Engine. 50-61
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Tulika Mitra, Tzi-cker Chiueh:
Dynamic 3D Graphics Workload Characterization and the Architectural Implications. 62-71
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Jesús Corbal, Roger Espasa, Mateo Valero:
Exploiting a New Level of DLP in Multimedia Applications. 72-79

Efficient Embedded Processors

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Sergei Y. Larin, Thomas M. Conte:
Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. 82-92
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Charles Lefurgy, Eva Piccininni, Trevor N. Mudge:
Evaluation of a High Performance Code Compression Method. 93-102
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Lea Hwang Lee, Jeff Scott, Bill Moyer, John Arends:
Low-Cost Branch Folding for Embedded Applications with Small Tight Loops. 103-111

Memory Hierarchy

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Santosh G. Abraham, Scott A. Mahlke:
Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems. 114-125
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Jamison D. Collins, Dean M. Tullsen:
Hardware Identification of Cache Conflict Misses. 126-135
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Sangyeun Cho, Pen-Chung Yew, Gyungho Lee:
Access Region Locality for High-Bandwidth Processor Memory System Design. 136-146
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Vijay S. Pai, Sarita V. Adve:
Code Transformations to Improve Memory Parallelism. 147-155

Better Scheduling

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Daniel A. Connors, Wen-mei W. Hwu:
Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results. 158-169
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Soner Önder, Rajiv Gupta:
Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing. 170-176
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Andreas Moshovos, Gurindar S. Sohi:
Read-After-Read Memory Dependence Prediction. 177-185
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Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
Delaying Physical Register Allocation through Virtual-Physical Registers. 186-192

Invited Speaker

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Bruce D. Shriver:
Core Technologies in Hardware and Software. 194-

Novel Microarchitectures and Multithreading

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Todd M. Austin:
DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. 196-207
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Mark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra:
Exploiting ILP in Page-based Intelligent Memory. 208-218
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Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi:
The Use of Multithreading for Exception Handling. 219-229
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Pedro Marcuello, Jordi Tubella, Antonio González:
Value Prediction for Speculative Multithreaded Architectures. 230-236

Low Power Enhancements

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Enric Musoll:
Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors. 238-247
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David H. Albonesi:
Selective Cache Ways: On-Demand Cache Resource Allocation. 248-259

Compilers

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Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey:
Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. 262-271
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Alexandre E. Eichenberger, Waleed Meleis:
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks. 272-283
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Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind:
Optimizations and Oracle Parallelism with Dynamic Translation. 284-295

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