"Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld ..."

Carlos Flores Fajardo et al. (2011)

> Home

Details and statistics

DOI: 10.1145/2024724.2024938

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/dac/FajardoFIGLZ11
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/dac/FajardoFIGLZ11
Carlos Flores Fajardo, Zhen Fang, Ravi R. Iyer, German Fabila Garcia, Seung Eun Lee, Li Zhao:
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms. DAC 2011: 966-971

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.