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ORCID24. ACM Great Lakes Symposium on VLSI 2017: Banff, AB, Canada
- Laleh Behjat, Jie Han, Miroslav N. Velev, Deming Chen:
Proceedings of the on Great Lakes Symposium on VLSI 2017, Banff, AB, Canada, May 10-12, 2017. ACM 2017, ISBN 978-1-4503-4972-7
Keynote & Invited Talks
- Leland Chang:
Cognitive Data-Centric Systems. 1 - Alex K. Jones:
Green Computing: New Challenges and Opportunities. 3 - Andrew Putnam:
FPGAs in the Datacenter: Combining the Worlds of Hardware and Software Development. 5 - Niraj K. Jha:
Internet-of-Medical-Things. 7 - Alex Bruton:
Designing Really Big Value Ideas. 9
Session 1: Emerging Technologies and Paradigms for Low Power Computing
- Pilin Junsangsri, Fabrizio Lombardi, Salin Junsangsri, Martin Margala
:
Design of a Low-Power Non-Volatile Programmable Inverter Cell for COGRE-based Circuits. 11-16 - Ali Murat Gok, Nikos Hardavellas:
VaLHALLA: Variable Latency History Aware Local-carry Lazy Adder. 17-22 - Hao Cai, You Wang, Lirida A. B. Naviner, Wang Kang, Weisheng Zhao:
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device. 23-28 - Xu He, Yao Wang, Yang Guo, Sorin Cotofana:
A Mixed-Size Monolithic 3D Placer with 2D Layout Inheritance. 29-34 - Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton:
LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. 35-40
Session 2: Design Techniques for Non-Traditional Computing
- Monther Abusultan, Sunil P. Khatri:
Design of a Flash-based Circuit for Multi-valued Logic. 41-46 - Weiqiang Liu, Jiahua Xu, Danye Wang, Fabrizio Lombardi:
Design of Approximate Logarithmic Multipliers. 47-52 - Amr M. S. Tosson, Shimeng Yu, Mohab H. Anis, Lan Wei:
Mitigating the Effect of Reliability Soft-errors of RRAM Devices on the Performance of RRAM-based Neuromorphic Systems. 53-58 - Yu Bai, X. Sharon Hu, Ronald F. DeMara, Mingjie Lin:
A Spin-Orbit Torque based Cellular Neural Network (CNN) Architecture. 59-64 - Michel A. Kinsy, Shreeya Khadka, Mihailo Isakov:
PreNoc: Neural Network based Predictive Routing for Network-on-Chip Architectures. 65-70
Session 3: Strategies for In-Memory Computing
- Jintao Yu, Tom Hogervorst, Razvan Nane:
A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons. 71-76 - Shaahin Angizi, Zhezhi He, Deliang Fan:
Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices. 77-82 - Zhezhi He, Shaahin Angizi, Farhana Parveen, Deliang Fan:
Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption. 83-88 - Yuanchang Chen, Yizhe Zhu, Fei Qiao, Jie Han, Yuansheng Liu, Huazhong Yang:
Evaluating Data Resilience in CNNs from an Approximate Memory Perspective. 89-94
Session 4: Circuits, Architectures, and System Level Issues for Many-Core Processors
- Kinshuk Sharma, Sunil P. Khatri:
A Robust C-element Design with Enhanced Metastability Performance. 95-100 - Abbas A. Fairouz, Monther Abusultan, Sunil P. Khatri:
Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors. 101-106 - Shoumik Maiti, Sudeep Pasricha:
DELCA: DVFS Efficient Low Cost Multicore Architecture. 107-112 - Abhishek Rajgadia, Newton, Virendra Singh:
EEAL: Processors' Performance Enhancement Through Early Execution of Aliased Loads. 113-118 - Daniel Olsen, Iraklis Anagnostopoulos:
Performance-Aware Resource Management of Multi-Threaded Applications on Many-Core Systems. 119-124
Session 5: CAD for the Nano Era
- Alex Vidal-Obiols, Jordi Cortadella, Jordi Petit:
Under-the-Cell Routing to Improve Manufacturability. 125-130 - Zhufei Chu, Xifan Tang, Mathias Soeken, Ana Petkovska, Grace Zgheib, Luca Gaetano Amarù, Yinshui Xia, Paolo Ienne, Giovanni De Micheli, Pierre-Emmanuel Gaillardon:
Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. 131-136 - Youngsoo Song, Jinwook Jung, Youngsoo Shin:
Redundant Via Insertion with Cut Optimization for Self-Aligned Double Patterning. 137-142 - Lucas Machado, Jordi Cortadella:
Boolean Decomposition for AIG Optimization. 143-148 - Chung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak:
Mixed-Cell-Height Standard Cell Placement Legalization. 149-154
Session 6: Hardware Security: New Advances in Timing Side Channel and Logic Obfuscation
- Fan Yao, Guru Venkataramani, Milos Doroslovacki:
Covert Timing Channels Exploiting Non-Uniform Memory Access based Architectures. 155-160 - Md Tanvir Arafin, Dhananjay Anand, Gang Qu:
A Low-Cost GPS Spoofing Detector Design for Internet of Things (IoT) Applications. 161-166 - Zhen Hang Jiang, Yunsi Fei, David R. Kaeli:
A Novel Side-Channel Timing Attack on GPUs. 167-172 - Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin:
Cyclic Obfuscation for Creating SAT-Unresolvable Circuits. 173-178 - Yuanqi Shen, Hai Zhou:
Double DIP: Re-Evaluating Security of Logic Encryption Algorithms. 179-184
Session 7: Testing and Reliability
- Ahish Mysore Somashekar, Spyros Tragoudas:
Efficient Critical Path Selection Under a Probabilistic Delay Model. 185-190 - Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. 191-196 - Yuwen Dave Lin, Charles H.-P. Wen, Herming Chiueh:
Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops. 197-202 - Luca Sterpone, Sarah Azimi, Boyang Du, David Merodio Codinachs, Raoul Grimoldi:
Effective Mitigation of Radiation-induced Single Event Transient on Flash-based FPGAs. 203-208 - Nikolaos Zompakis, Michail Noltsis, Dimitrios Rodopoulos, Francky Catthoor, Dimitrios Soudris:
Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference. 209-214
Session 8: Emerging Technologies, RF Circuits and Security Functions
- Joshua Potter, William H. Grover, Philip Brisk:
Design Automation for Paper Microfluidics with Passive Flow Substrates. 215-220 - Md. Amimul Ehsan, Zhen Zhou, Yang Yi:
Neuromorphic 3D Integrated Circuit: A Hybrid, Reliable and Energy Efficient Approach for Next Generation Computing. 221-226 - Dimo Martev, Sven Hampel, Ulf Schlichtmann:
A Method for Phase Noise Analysis of RF Circuits. 227-231 - Leonid Azriel, Ran Ginosar, Avi Mendelson:
Revealing On-chip Proprietary Security Functions with Scan Side Channel Based Reverse Engineering. 233-238
Session 9: CAD under Challenges: Tight Constraints and Unreliability
- Ghaith Kazma, Ghaith Bany Hamad, Otmane Aït Mohamed, Yvon Savaria:
Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories. 239-244 - Shuang Song, Raj Desikan, Mohamad Barakat, Sridhar Sundaram, Andreas Gerstlauer, Lizy K. John:
Fine-Grain Program Snippets Generator for Mobile Core Design. 245-250 - Jack S.-Y. Lin, Louis Y.-Z. Lin, Ryan H.-M. Huang, Charles H.-P. Wen:
Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax? 251-256 - Shi Sha, Wujie Wen, Shaolei Ren, Gang Quan:
A Thermal-Balanced Variable-Sized-Bin-Packing Approach for Energy Efficient Multi-Core Real-Time Scheduling. 257-262 - Weichen Liu, Peng Wang, Mengquan Li, Yiyuan Xie, Nan Guan:
Quantitative Modeling of Thermo-Optic Effects in Optical Networks-on-Chip. 263-268
Session 10: Memory Design from Circuits to Architectures
- Samira Ataei, James E. Stine:
A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time. 269-274 - Lei Jiang, Sparsh Mittal, Wujie Wen:
Building a Fast and Power Efficient Inductive Charge Pump System for 3D Stacked Phase Change Memories. 275-280 - Chaobing Zhou, Libo Huang, Zhisheng Li, Tan Zhang, Qiang Dou:
Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM. 281-286 - Peng Ouyang, Shouyi Yin, Chunxiao Xing, Leibo Liu, Shaojun Wei:
A Power Efficient Architecture with Optimized Parallel Memory Accessing for Feature Generation. 287-292 - Linbin Chen, Fabrizio Lombardi, Paolo Montuschi, Jie Han, Weiqiang Liu:
Design of Approximate High-Radix Dividers by Inexact Binary Signed-Digit Addition. 293-298
Special Session 1: Low Power Computing based on Non-Volatile Memories
- Wang Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang, Weisheng Zhao:
Advanced Low Power Spintronic Memories beyond STT-MRAM. 299-304 - Robert Perricone, Li Tang, Michael T. Niemier, Xiaobo Sharon Hu:
Exploiting Non-Volatility for Information Processing. 305-310 - Zixuan Chen, Huaqiang Wu, Bin Gao, Peng Yao, Xinyi Li, He Qian:
Neuromorphic Computing based on Resistive RAM. 311-315 - Adrien F. Vincent, Nicolas Locatelli, Qifan Wu, Damien Querlioz:
Implications of the Use of Magnetic Tunnel Junctions as Synapses in Neuromorphic Systems. 317-320
Special Session 2: Three-Dimensional Integrated Circuit (3D IC) Security
- Jaya Dofe, Peng Gu, Dylan C. Stow, Qiaoyan Yu, Eren Kursun, Yuan Xie:
Security Threats and Countermeasures in Three-Dimensional Integrated Circuits. 321-326 - Jaya Dofe, Zhiming Zhang, Qiaoyan Yu, Chen Yan, Emre Salman:
Impact of Power Distribution Network on Power Analysis Attacks in Three-Dimensional Integrated Circuits. 327-332 - Mohamed El Massad, Frank Imeson, Siddharth Garg, Mahesh Tripunitara:
The Need for Declarative Properties in Digital IC Security. 333-338 - Qihang Shi, Kan Xiao, Domenic Forte, Mark Tehranipoor:
Securing Split Manufactured ICs with Wire Lifting Obfuscated Built-In Self-Authentication. 339-344
Special Session 3: Logic Obfuscation for IoT Security: A New Arms Race?
- Xueyan Wang, Qiang Zhou, Yici Cai, Gang Qu:
An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack. 345-350 - Muhammad Yasin, Abhrajit Sengupta, Benjamin Carrión Schäfer, Yiorgos Makris, Ozgur Sinanoglu, Jeyavijayan Rajendran:
What to Lock?: Functional and Parametric Locking. 351-356 - Kaveh Shamsi, Meng Li, Travis Meade, Zheng Zhao, David Z. Pan, Yier Jin:
Circuit Obfuscation and Oracle-guided Attacks: Who can Prevail? 357-362 - Sarah Amir, Bicky Shakya, Domenic Forte, Mark Tehranipoor, Swarup Bhunia:
Comparative Analysis of Hardware Obfuscation for IP Protection. 363-368
Special Session 4: Efficient IoT Systems: The Power of Heterogenous Integration
- Selçuk Köse:
Efficient and Secure On-Chip Reconfigurable Voltage Regulation for IoT Devices. 369-374 - Caleb Serafy, Zhiyuan Yang, Ankur Srivastava:
Design Space Modeling and Simulation for Physically Constrained 3D CPUs. 375-380 - Inna Partin-Vaisband:
Automated Design of Stable Power Delivery Systems for Heterogeneous IoT Systems. 381-386 - Divya Pathak, Houman Homayoun, Ioannis Savidis:
Work Load Scheduling For Multi Core Systems With Under-Provisioned Power Delivery. 387-392 - Elisa Vianello, Thilo Werner, Alessandro Grossi, Etienne Nowak, Barbara De Salvo, Luca Perniola, Olivier Bichler, Blaise Yvert:
Bioinspired Programming of Resistive Memory Devices for Implementing Spiking Neural Networks. 393-398
Poster Session I
- Kuen-Wey Lin, Yeh-Sheng Lin, Yih-Lang Li, Rung-Bin Lin:
A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points. 399-402 - Xiaodong Xu, Qi Xu, Jinglei Huang, Song Chen:
An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs. 403-406 - Kalindu Herath, Alok Prakash, Guiyuan Jiang, Thambipillai Srikanthan:
Communication-aware Partitioning for Energy Optimization of Large FPGA Designs. 407-410 - Yong Chen, Emil Matús, Gerhard P. Fettweis:
Combined Centralized and Distributed Connection Allocation in Large TDM Circuit Switching NoCs. 411-414 - Xiang Lin, R. D. (Shawn) Blanton, Donald E. Thomas:
Random Forest Architectures on FPGA for Multiple Applications. 415-418 - Wooseok Lee, Dam Sunwoo, Christopher D. Emmons, Andreas Gerstlauer, Lizy K. John:
Exploring Heterogeneous-ISA Core Architectures for High-Performance and Energy-Efficient Mobile SoCs. 419-422 - Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois:
An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search. 423-426 - Huimei Cheng, Ji Li, Jeffrey T. Draper, Shahin Nazarian, Yanzhi Wang:
Deadline-Aware Joint Optimization of Sleep Transistor and Supply Voltage for FinFET Based Embedded Systems. 427-430 - Rajsaktish Sankaranarayanan, Matthew R. Guthaus:
Energy Savings and Performance Improvement in Subthreshold Using Adaptive Body Bias. 431-434 - Xuncheng Zou, Bo Liu, Shigetoshi Nakatake:
Low Voltage Stochastic Flash ADC with Front-end of Inverter-based Comparative Unit. 435-438 - Gyunam Jeon, Yong-Bin Kim:
Switched Capacitor and Infinite Impulse Response Summation for a Quarter-Rate DFE with 4Gb/s Data Rate. 439-442 - Ridvan Umaz, Lei Wang:
An Energy Combiner Design for Multiple Microbial Energy Harvesting Sources. 443-446
Poster Session II
- Lingxuan Shao, Yibin Yang, Hailong Yao, Tsung-Yi Ho, Yici Cai:
LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips. 447-450 - Liang Wang, Xiaohang Wang, Ho-fung Leung, Terrence S. T. Mak:
Throughput Optimization for Lifetime Budgeting in Many-Core Systems. 451-454 - Sarmad Tanwir, Michael S. Hsiao, Loganathan Lingappan:
A Test Pattern Quality Metric for Diagnosis of Multiple Stuck-at and Transition faults. 455-458 - Brian Crites, Karen Kong, Philip Brisk:
Reducing Microfluidic Very Large Scale Integration (mVLSI) Chip Area by Seam Carving. 459-462 - Arun Chandrasekharan, Daniel Große, Rolf Drechsler:
ProACt: A Processor for High Performance On-demand Approximate Computing. 463-466 - Zihao Yuan, Ji Li, Zhe Li, Caiwen Ding, Ao Ren, Bo Yuan, Qinru Qiu, Jeffrey Draper, Yanzhi Wang:
Softmax Regression Design for Stochastic Computing Based Deep Convolutional Neural Networks. 467-470 - Sayed Ahmad Salehi, Yin Liu, Marc D. Riedel, Keshab K. Parhi:
Computing Polynomials with Positive Coefficients using Stochastic Logic by Double-NAND Expansion. 471-474 - Pai-Shun Ting, John P. Hayes:
On the Role of Sequential Circuits in Stochastic Computing. 475-478 - Sagarvarma Sayyaparaju, Gangotree Chakma, Sherif Amer, Garrett S. Rose:
Circuit Techniques for Online Learning of Memristive Synapses in CMOS-Memristor Neuromorphic Systems. 479-482 - Sean Kramer, Zhiming Zhang, Jaya Dofe, Qiaoyan Yu:
Mitigating Control Flow Attacks in Embedded Systems with Novel Built-in Secure Register Bank. 483-486 - Shuyu Kong, Yuanqi Shen, Hai Zhou:
Using Security Invariant To Verify Confidentiality in Hardware Design. 487-490 - Qutaiba Alasad, Jiann-Shiun Yuan, Deliang Fan:
Leveraging All-Spin Logic to Improve Hardware Security. 491-494
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