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ORCID37th ISCA 2010: Saint-Malo, France
- André Seznec, Uri C. Weiser, Ronny Ronen:
37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. ACM 2010, ISBN 978-1-4503-0053-7
Keynote
- William J. Dally:
Moving the needle, computer architecture research in academe and industry. 1
Energy efficiency
- Yasuko Watanabe, John D. Davis, David A. Wood:
WiDGET: Wisconsin decoupled grid execution tiles. 2-13 - Dan Gibson, David A. Wood:
Forwardflow: a scalable core for power-constrained CMPs. 14-25 - Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz:
Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis. 26-36 - Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz:
Understanding sources of inefficiency in general-purpose chips. 37-47
Caches
- Thomas W. Barr, Alan L. Cox, Scott Rixner:
Translation caching: skip, don't walk (the page table). 48-59 - Aamer Jaleel, Kevin B. Theobald, Simon C. Steely Jr., Joel S. Emer:
High performance cache replacement using re-reference interval prediction (RRIP). 60-71 - Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John:
The virtual write queue: coordinating DRAM and last-level cache policies. 72-82 - Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu:
Reducing cache power with low-cost, multi-bit error-correcting codes. 83-93
Emerging technologies and interconnect
- Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun Hu, Shang Wang, Ioannis Savidis, Manish Jain, Rebecca Berman, Peng Liu, Michael C. Huang
, Hui Wu, Eby G. Friedman, Gary Wicks, Duncan Moore:
An intra-chip free-space optical interconnect. 94-105 - Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das:
Aérgia: exploiting packet latency slack in on-chip networks. 106-116 - Pranay Koka, Michael O. McCracken, Herb Schwetman, Xuezhe Zheng, Ron Ho, Ashok V. Krishnamoorthy:
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems. 117-128 - Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic:
Re-architecting DRAM memory systems with monolithically integrated silicon photonics. 129-140
Memory subsystems
- Stuart E. Schechter, Gabriel H. Loh, Karin Strauss, Doug Burger:
Use ECP, not ECC, for hard failures in resistive memories. 141-152 - Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño, John P. Karidis:
Morphable memory system: a robust architecture for exploiting multi-level phase change memories. 153-162 - Timothy Pritchett, Mithuna Thottethodi:
SieveStore: a highly-selective, ensemble-level disk cache for cost-performance. 163-174 - Aniruddha N. Udipi, Naveen Muralimanohar, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi:
Rethinking DRAM design and organization for energy-constrained multi-cores. 175-186
Productivity and debugging
- Yunji Chen, Weiwu Hu, Tianshi Chen, Ruiyang Wu:
LReplay: a pending period based deterministic replay scheme. 187-197 - Gwendolyn Voskuilen, Faraz Ahmad, T. N. Vijaykumar:
Timetraveler: exploiting acyclic races for optimizing memory race recording. 198-209 - Brandon Lucia, Luis Ceze, Karin Strauss, Shaz Qadeer, Hans-Juergen Boehm:
Conflict exceptions: simplifying concurrent language semantics with precise hardware exceptions for data-races. 210-221 - Brandon Lucia, Luis Ceze, Karin Strauss:
ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations. 222-233
Keynote
- Mary Jane Irwin:
Shared caches in multicores: the good, the bad, and the ugly. 234
Acceleration architecture
- Jiayuan Meng, David Tarjan, Kevin Skadron:
Dynamic warp subdivision for integrated branch and memory divergence tolerance. 235-246 - Srimat T. Chakradhar, Murugan Sankaradass, Venkata Jakkula, Srihari Cadambi:
A dynamically configurable coprocessor for convolutional neural networks. 247-257
Threading
- Colin Blundell, Arun Raghavan, Milo M. K. Martin:
RETCON: transactional repair without replay. 258-269 - Janghaeng Lee, Haicheng Wu, Madhumitha Ravichandran, Nathan Clark:
Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications. 270-279
Simulation technologies and real system evaluation
- Sunpyo Hong, Hyesoon Kim:
An integrated GPU power and performance model. 280-289 - Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson:
A case for FAME: FPGA architecture model execution. 290-301 - Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge, Krisztián Flautner:
Evolution of thread-level parallelism in desktop applications. 302-313
Cluster and data center
- Vijay Janapa Reddi, Benjamin C. Lee, Trishul M. Chilimbi, Kushagra Vaid:
Web search using mobile cores: quantifying and mitigating the price of efficiency. 314-325 - Vijayaraghavan Soundararajan, Jennifer M. Anderson:
The impact of management operations on the virtualized datacenter. 326-337 - Dennis Abts, Michael R. Marty, Philip M. Wells, Peter Klausler, Hong Liu:
Energy proportional datacenter networks. 338-347
Keynote
- Charles P. Thacker:
Improving the future by examining the past. 348 - Olivier Temam:
The rebirth of neural networks. 349
QOB
- Eric Keller, Jakub Szefer, Jennifer Rexford, Ruby B. Lee:
NoHype: virtualized cloud infrastructure without the virtualization. 350-361 - Stijn Eyerman, Lieven Eeckhout:
Modeling critical sections in Amdahl's law and its implications for multicore design. 362-370 - Xiaochen Guo, Engin Ipek, Tolga Soyata:
Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing. 371-382
Security
- Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee:
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. 383-394 - Ruirui C. Huang, G. Edward Suh:
IVEC: off-chip memory integrity protection for both security and reliability. 395-406 - Arrvindh Shriraman, Sandhya Dwarkadas:
Sentry: light-weight auxiliary memory access control. 407-418
Multi-core
- Enric Herrero, José González, Ramon Canal:
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors. 419-428 - John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel:
Cohesion: a hybrid memory model for accelerators. 429-440 - M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt:
Data marshaling for multi-core architectures. 441-450 - Victor W. Lee, Changkyu Kim, Jatin Chhugani, Michael Deisher, Daehyun Kim, Anthony D. Nguyen, Nadathur Satish, Mikhail Smelyanskiy, Srinivas Chennupaty, Per Hammarlund, Ronak Singhal, Pradeep Dubey:
Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. 451-460
Reliability and fault-tolerance
- Vilas Sridharan, David R. Kaeli:
Using hardware vulnerability factors to enhance AVF analysis. 461-472 - Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke:
Necromancer: enhancing system throughput by animating dead cores. 473-484 - Guihai Yan, Xiaoyao Liang, Yinhe Han, Xiaowei Li:
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. 485-496 - Marc de Kruijf, Shuou Nomura, Karthikeyan Sankaralingam:
Relax: an architectural framework for software recovery of hardware faults. 497-508
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