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Journal of Signal Processing Systems, Volume 85

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Volume 85, Number 1, October 2016

Design and Implementation of DSP Systems

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Warren J. Gross, Zhiyuan Yan:
Guest Editorial: Design and Implementation of DSP Systems. 1-3
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Ubaid Ahmad, Min Li, Amir Amin, Meng Li, Liesbet Van der Perre, Rudy Lauwereins, Sofie Pollin:
An Energy-Efficient Reconfigurable ASIP Supporting Multi-mode MIMO Detection. 5-21
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Stavros Tripakis, Rhishikesh Limaye, Kaushik Ravindran, Guoqiang Wang, Hugo A. Andrade, Arkadeb Ghosal:
Tokens vs. Signals: On Conformance between Formal Models of Dataflow and Hardware. 23-43
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Ricardo S. Ferreira, Waldir Denver, Monica Magalhães Pereira, Stephan Wong, Carlos Arthur Lang Lisbôa, Luigi Carro:
A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility. 45-66
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Berkin Akin, Franz Franchetti, James C. Hoe:
FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation. 67-82
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Nico Mentzer, Guillermo Payá-Vayá, Holger Blume:
Analyzing the Performance-Hardware Trade-off of an ASIP-based SIFT Feature Extraction. 83-99
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Juha Yli-Kaakinen, Markku Renfors:
Optimization of Flexible Filter Banks Based on Fast Convolution. 101-111
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Riham Nehmeh, Daniel Ménard, Erwan Nogues, Andrei Banciu, Thierry Michel, Romuald Rocher:
Fast Integer Word-length Optimization for Fixed-point Systems - Integer Word-length Optimization. 113-128
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Christian Senning, Georgios Karakonstantis, Andreas Burg:
Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems. 129-142
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Carlo Sau, Paolo Meloni, Luigi Raffo, Francesca Palumbo, Endri Bezati, Simone Casale Brunet, Marco Mattavelli:
Automated Design Flow for Multi-Functional Dataflow-Based Platforms. 143-165
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Mona Aghababaeetafreshi, Lasse Lehtonen, Toni Levanen, Mikko Valkama, Jarmo Takala:
IEEE 802.11ac MIMO Transceiver Baseband Processing on a VLIW Processor. 167-182

Volume 85, Number 2, November 2016

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Arsalan Saeed, Efstathios Katranaras, Mehrdad Dianati, Muhammad Ali Imran:
Control and Data Channel Resource Allocation in OFDMA Heterogeneous Networks. 183-199
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Amin Jarrah, Mohsin M. Jamali:
A Parallel Implementation of Extensive Cancellation Algorithm (ECA) for Passive Bistatic Radar (PBR) on a GPU. 201-209
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Ji-Hun Mun, Yo-Sung Ho:
Multi-directional Hole Filling Method for Virtual View Synthesis. 211-219
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Jin Huang, Weidong Jin, Duo Zhao, Na Qin, Qi Li:
Double-Trapezium Cylinder Codebook Model Based on YUV Color Model for Foreground Detection with Shadow and Highlight Suppression. 221-233
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Sana Abid Khan, Shahzad Amin Sheikh:
Design and Implementation of a Blind Adaptive Equalizer Using Frequency Domain Improved Square Contour Algorithm. 235-247
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Chao-Feng Tseng, Yen-Tai Lai:
A High-Throughput JPEG XR Encoder. 249-261
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Selvakumar Karuppusamy, Jovitha Jerome, Kumar T. Rajamani, Nishanth Shankar:
Real-Time Vision Based Driver Drowsiness Detection Using Partial Least Squares Analysis. 263-274
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Jiwon Choi, Changick Kim:
Sparse Seam-Carving for Structure Preserving Image Retargeting. 275-283

Volume 85, Number 3, December 2016

Application-Specific Architectures and Processors

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Editorial Note. 285
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Hamed Tabkhi, Robert Bushey, Gunar Schirner:
Function-Level Processor (FLP): A Novel Processor Class for Efficient Processing of Streaming Applications. 287-306
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Heiner Giefers, Raphael Polig, Christoph Hagleitner:
Measuring and Modeling the Power Consumption of Energy-Efficient FPGA Coprocessors for GEMM and FFT. 307-323
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Francesco Conti, Andrea Marongiu, Chuck Pilkington, Luca Benini:
He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores. 325-340
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Waqar Hussain, Roberto Airoldi, Henry Hoffmann, Tapani Ahonen, Jari Nurmi:
HARP2: An X-Scale Reconfigurable Accelerator-Rich Platform for Massively-Parallel Signal Processing Algorithms. 341-353
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Kubilay Atasu:
Feature-rich Regular Expression Matching Accelerator for Text Analytics. 355-371
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Konstantinos Krommydas, Wu-chun Feng, Christos D. Antonopoulos, Nikolaos Bellas:
OpenDwarfs: Characterization of Dwarf-Based Benchmarks on Fixed and Reconfigurable Architectures. 373-392

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