Hans Hasselby-Andersen

Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. TT-Ascalon is Tenstorrent’s high-performance RISC-V CPU, built on open standards to provide maximum flexibility and architectural control. It is based on the open RISC-V ISA and is RVA23 compliant. A central focus of the Ashling–Tenstorrent collaboration is comprehensive trace support, built on the RISC-V standard N-Trace architecture. RiscFree integrates with Tenstorrent’s Ascalon CPUs to capture detailed trace data across multi-core systems, enabling real-time visibility into instruction execution, memory transactions, and key system events. In addition to N-Trace, Tenstorrent’s Debug Signal Trace (DST) infrastructure has been fully implemented in its Ascalon CPUs, providing access to critical micro-architectural signals alongside standard trace data during post-silicon validation. DST enhances debugging, performance analysis, and coverage, and is fully supported by Ashling’s RiscFree tools—enabling deep trace visibility with minimal integration overhead. Learn more here: https://lnkd.in/gthF_9uj #RISCVEverwhere #DEBUG #Tenstorrent

428

5 Kommentarer

This Virtium Embedded Artists AB solution represents an architecture-first approach to EdgeAI, enabling customers to start with a general-purpose SoM and seamlessly upgrade to AI without hardware redesign. The design allows initial adoption by those who don't yet need AI, but when ready, the same system can be enhanced with EdgeAI by simply replacing the SoM ,no board modifications or hardware changes required. This flexibility significantly lowers barriers to AI adoption and exemplifies genuine innovation in modular embedded system design . Read the PR : https://lnkd.in/dRSG3ivz Renesas Electronics RZ/G3E + DEEPX : https://lnkd.in/dehm9mbM Renesas Electronics RZ/G3E : https://lnkd.in/eWhPwAWz Gary Drossel David Beasley Anders Rosvall Phu Hoang Stefano Tansini Carmelo Sansone Andrea Franza Leisha Li (Changhong Li) Rod Ghavami Brian Witzen Casey O'Grady

92

MAJOR ADVANCES IN (AI) TESTING DEMONSTRATED AT ECOC Exhibition 2025. I enjoyed a fascinating 3-way discussion about testing on the exhibition floor this week. Photonic integrated circuits operate at very high frequencies. We see InP and TFLN operating up to 110 GHz. Manufacturing is done at the wafer level, so we need to find partners who can test at such high frequencies, preferably automatically. In the video below, we discussed first with Lawrence van der Vegt, Head of Photonics at MPI Corporation. Founded in 1995 and headquartered in Hsinchu, Taiwan, MPI Corporation is a global technology leader in the testing of Semiconductors, Light Emitting Diodes, Photo Detectors, Lasers, Materials Research, and more. In September 2025, they announced the release of a fully integrated 250 GHz broadband test solution for the new Keysight Technologies NA5305A/7A PNA-X Frequency Extender. It builds on their deep expertise in sub-terahertz probing and on-wafer measurements. We explored why this is needed now. We also hear from Amir H. Ghadimi, CEO of Lightium based in Zurich, Switzerland. He explains what they need from an end-user perspective.  He also comments on a partnership between MPI Corporation and Axiomatic_AI. Design Engineer Mahdi Safari explains how their AI-driven SmartMeasure system utilises natural language to configure the probe station, select devices, and optimise the measurement order to maximise information retrieval. MPI tell me they have a lot of new developments on their roadmap to share at the OFC Conference 2026 and in Malaga next year. Onward to meet other Optica Corporate Members exhibiting this year and with a powerful deep-tech story to share! Does that apply to your company too? Join Optica and let's discuss.

129

4 Kommentarer

Is There Still A Future For Hard Disk Drives? The cost of HDDs and SSDs will continue to fall, while capacity will continue to increase in both. The capacity for solid state drives (#SSDs) keeps going up while the price per terabyte keeps falling, sometimes raising questions about the future for hard disk drives (#HDDs). Will the cost of #SSDs per TB eventually become so low that they will totally displace HDDs? Barry Pangrle decided to ask a couple of experts in the field, Jim Handy from Objective Analysis and Thomas Coughlin of Coughlin Associates. He was looking for a comparison projection for HDDs and SSDs that would go about five years out into the future. Jim had performed such an exercise back in 2017, WDC: No SSD/HDD Crossover,but I needed something more recent. Jim had his SSD forecast data, shown in red in Figure 1 and Tom provided the HDD data shown in blue. The slope is steeper for the #SSD data, but it does not look like we’ll see a crossover in the next 5 years. The green $4.75/TB point was placed there by Barry to show readers where that falls on the plot and to use again later in another chart.... A very big thank you to Barry Pangrle , Jim Handy , Thomas Coughlin and Semiconductor Engineering for this very interesting full comparison/article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eKTxfR7P #semiconductorindustry #semiconductor #technology #tech #chip #chips #it #datacenter #technology #memory #storage #computer #ssd #hdd

88

4 Kommentarer

UBM (Under Bump Metallization) Purpose: UBM is a critical layer in advanced semiconductor packaging, enabling reliable electrical and mechanical connections between the chip and solder bumps or copper pillars. Functions: Provides electrical interconnection, wetting for solder, diffusion barrier, and mechanical support. Prevents failures like delamination, solder voids, and electromigration. Applications: Used in Flip-Chip, Wafer-Level Packaging (WLP), Fan-Out WLP, 2.5D/3D IC stacking, and high-end 3D packaging (e.g., HBM, CoWoS). Materials: Multi-layer stacks: adhesion (Ti, TiW, Ta), seed/conductor (Cu), barrier (TiN, Ta, Ni), wetting (Au, Ag), and solder (Sn, SnAgCu). Etching: Selective etchants are used for each metal layer (e.g., HF+H₂O₂ for Ti, H₃PO₄+H₂O₂ for Cu, KI/I₂ for Au). Process control is crucial to avoid over-etching and ensure pad accuracy. Trends: Moving toward finer pitches (<50 μm), eco-friendly chemistries, cost reduction (less Au), and dry/plasma etching for better precision. Conclusion: UBM is foundational for next-gen semiconductor reliability, yield, and performance, especially as packaging becomes more complex and dense.

251

3 Kommentarer

TSMC Broke Up with GaN. Now It's All About Advanced Packaging. After years of investing in Gallium Nitride (GaN), TSMC just walked away, reassigning its GaN fab space to focus on CoWoS and 3D ICs. No warning. Just: “It’s not you, it’s advanced packaging.” Meanwhile… SiC is waiting in the wings. “Hey GaN, if you like high voltage and long drives, call me. The EV crowd loves me.” In semiconductors, even the materials have relationship drama.

59

6 Kommentarer