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STM32U5
DMA: DMA transfers
hardware and software views
Rev 1.0

• The request that initiates a DMA transfer may be:
• A hardware request from a peripheral configured in DMA mode (for a transfer from/to the
peripheral data register to/from memory)
• A hardware request from a peripheral to update its control register(s) from memory
• A hardware request from a peripheral to read of its status register(s) to memory
• A software request typically from the CPU for a data transfer from a memory-mapped address to
another memory mapped address
DMA requested transfer
2

Queue 0 RRA
• DMA arbitration and bandwidth are guaranteed with:
• An equal maximum bandwidth between requests with a same priority
• A reserved bandwidth to the time-sensitive requests, i.e. with the highest priority 3
• A residual weighted bandwidth between different low-priority requests (respectively lowest
priority 0 vs priority 1 vs priority 2)
• The different weights are monotonically resulting from the programmed channel priorities
DMA request arbitration
3
Queue 1 RRA
Queue 2 RRA
Queue 3 RRA
RRA
FPA
Request from any channel x being assigned with
DMA_CxCR[PRIO]=0
Request from any channel x being assigned with
DMA_CxCR[PRIO]=1
Request from any channel x being assigned with
DMA_CxCR[PRIO]=2
Request from any channel x being assigned with
DMA_CxCR[PRIO]=3
DMA arbitration
Granted request
Low priority
High priority
RRA= Round-Robin Arbitration
FPA: Fixed-Priority Arbitration
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