[VHDL+Verilog]两种语言分别设计的FIFO源码.zip

[VHDL+Verilog]两种语言分别设计的FIFO源码： ch_fifo.v fifo_2048x8.v fifo_status.v pn_correlation.v pn_correlation_fsm.v pn_correlator.v module ch_fifo(rd_clk, wr_clk, reset, data_ch, rd_data, rd, pn_lock_rd_clk, almost_full, almost_empty, full, empty); input rd_clk, wr_clk, reset, data_ch, rd; output pn_lock_rd_clk, almost_full, almost_empty, full, empty; output [7:0] rd_data; wire pn_lock, wr, wr_addr_srst; wire [10:0] rd_addr, wr_addr; wire [7:0] wr_data; pn_correlator pn_correlator_inst (.clk(wr_clk), .reset(reset), .data_ch(data_ch), .wr_data(wr_data), .wr(wr), .pn_lock(pn_lock), .wr_addr_srst(wr_addr_srst)); fifo_status fifo_status_inst (.rd_clk(rd_clk), .wr_clk(wr_clk), .reset(reset), .pn_lock(pn_lock), .rd_addr(rd_addr), .wr_addr_srst(wr_addr_srst), .wr_addr(wr_addr), .wr(wr), .rd(rd), .almost_full(almost_full), .almost_empty(almost_empty), .full(full), .empty(empty), .pn_lock_rd_clk(pn_lock_rd_clk)); fifo_2048x8 fifo_2048x8_inst (.rd_clk(rd_clk), .wr_clk(wr_clk), .wr(wr), .rd(rd), .reset(reset), .wr_addr(wr_addr), .rd_addr(rd_addr), .wr_data(wr_data), .rd_data(rd_data)); endmodule // ch_fifo