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f1高度855px,f2高度55px, 当f3高度为100%时,
如何才能让f3是占f1的剩余高度,而不是f1的高度
浏览:2

STM8L Training Slides
MMS – MCD
Application Team

2
Advanced Control And General Purpose
Timers

3
CH3
CH2N
CH2
CH1
CH1N
Features overview
• 16-bit Counter
– Auto Reload
– Up, down and center-aligned modes
• 4 x 16 High resolution Capture Compare
channels
– Programmable direction of the channel:
input/output
– Output Compare: Toggle, PWM
– Input Capture
– PWM Input Capture
• Synchronization between Timers
• Up to 8 interrupts and up to 6 DMA requests
• Motor Control Specific Features
• OC Signal Management
– Complementary outputs on three channels
– Dead-time management
– Repetition Unit
• Encoder Interface
• Embedded Safety features
– Break sources: BKIN pin / comparator 2 output
– Lockable unit configuration
16-Bit Prescaler
Trigger/Clock
Controller
Trigger
Output
Clock
Auto Reload REG
+/- 16-Bit Counter
Capture Compare
Capture Compare
Capture Compare
Capture Compare
ETR
ITR 3
ITR 2
ITR 1
BKIN
CH1
CH2
CH3
CH3N
Break from COMP2

4
Interrupts request sources
• 8 Interrupt request sources mapped on
3 interrupt vectors:
– Break input
– Trigger event
– Update event (overflow,
underflow…)
– Commutation event
– Capture / compare 1 event
– Capture / compare 2 event
– Capture / compare 3 event
– Capture / compare 4 event
Break Interrupt Enable
Break Flag status
TO IRQ Handler N°17
TO IRQ Handler N°23
Interrupt Enable
Trigger/Update/Commutation
Flag status
Capture/Compare
Interrupt Enable
Capture/Compare
Flag status
TO IRQ Handler N°24

5
DMA capability
• 6 DMA request sources:
– Commutation event
– Capture / Compare 1 event
– Capture / Compare 2 event
– Capture / Compare 3 event
– Capture / Compare 4 event
– Update event (overflow, underflow…)
• 2 DMA modes:
– Single mode: single register is transferred to or from a single TIM register
– Burst mode: block of timer registers is transferred
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