PCIExpressCEMSpecification1.1(英文版,共90页)资源-CSDN下载

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### PCI Express CEM Specification 1.1 知识点概览 #### 1. 引言与概述 **PCI Express CEM（Card Electromechanical）Specification 1.1** 是一个重要的技术文档，用于定义PCI Express卡在机械、电气方面的设计规范。尽管PCI 2.0/2.1标准已经发布，但在实际应用中仍有很多基于PCIe 1.0/1.1的设备在使用。这份文档对于理解早期PCI Express技术以及维护旧系统至关重要。该文档最初发布于2002年7月22日，并在后续进行了多次修订，最终版本1.1发布于2005年3月28日。它详细介绍了PCI Express卡的设计规范，包括机械结构、电气特性等方面的要求，确保不同厂商生产的PCI Express设备能够兼容互用。 #### 2. 相关知识点详解 ##### 2.1 参考时钟 REFCLK - **低电压摆幅差分时钟**: REFCLK采用低电压摆幅差分信号，以提高信号质量和抗干扰能力。 - **展频时钟 SSC (Spread Spectrum Clocking)**: 为了减少电磁干扰(EMI)，REFCLK可以采用展频时钟技术，在一定频率范围内变化时钟频率。 - **REFCLK AC 规格**: 对REFCLK的交流特性进行了详细规定，包括频率稳定性、幅度、上升时间等参数。 - **REFCLK相位抖动规格**: 定义了REFCLK的最大允许相位抖动范围，这对于保证数据传输的可靠性非常重要。 ##### 2.2 PERST# 信号 - **初始上电 (G3 to L0)**: 当设备上电时，PERST#信号会被激活以复位PCI Express设备。 - **电源管理状态 (S0 to S3/S4 to S0)**: 在不同的电源管理状态下，PERST#信号的行为有所不同，以适应不同的节能需求。 - **下电**: 在设备关闭或进入休眠模式时，PERST#信号被用来通知系统进行适当的处理。 ##### 2.3 WAKE# 信号 WAKE# 信号主要用于实现PCI Express设备的唤醒功能。当连接的设备检测到特定条件时，可以通过拉低WAKE#信号来唤醒主机系统。 ##### 2.4 SMBUS (可选) SMBUS是系统管理总线(System Management Bus)的一种形式，提供了一种简单的方法来监控计算机系统的组件状态。在某些PCI Express卡中，可能会包含SMBUS接口，以支持额外的功能。 #### 3. 机械概述文档还涵盖了PCI Express卡的机械设计要求，包括尺寸、连接器布局、安装孔位置等细节。这些要求确保了不同厂商生产的产品能够相互兼容，并且能够在各种类型的系统中正确安装。 #### 4. 结论 PCI Express CEM Specification 1.1 是一个重要的参考文档，对于设计、生产和使用基于PCI Express 1.0/1.1标准的设备至关重要。通过遵循这些规范，可以确保设备在各种环境中稳定运行，并与其他设备兼容。此外，这份文档还为用户提供了关于如何正确使用和维护PCI Express设备的指导，有助于延长设备的使用寿命并提高其性能。

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PCI Express

™

Card Electromechanical

Specification

Revision 1.1

March 28, 2005

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1

Contents

1. INTRODUCTION....................................................................................................................7

1.1. TERMS AND DEFINITIONS ..................................................................................................... 7

1.2. REFERENCE DOCUMENTS ..................................................................................................... 9

1.3. SPECIFICATION CONTENTS................................................................................................... 9

1.4. OBJECTIVES............................................................................................................................. 10

1.5. ELECTRICAL OVERVIEW ..................................................................................................... 10

1.6. MECHANICAL OVERVIEW ................................................................................................... 11

2. AUXILIARY SIGNALS........................................................................................................13

2.1. REFERENCE CLOCK............................................................................................................... 14

2.1.1. Low Voltage Swing, Differential Clocks .................................................................... 14

2.1.2. Spread Spectrum Clocking (SSC)............................................................................... 15

2.1.3. REFCLK AC Specifications........................................................................................ 16

2.1.4. REFCLK Phase Jitter Specification ........................................................................... 19

2.2. PERST# SIGNAL ...................................................................................................................... 20

2.2.1. Initial Power-Up (G3 to L0)....................................................................................... 20

2.2.2. Power Management States (S0 to S3/S4 to S0) .......................................................... 21

2.2.3. Power Down............................................................................................................... 22

2.3. WAKE# SIGNAL ...................................................................................................................... 24

2.4. SMBUS (OPTIONAL)............................................................................................................... 27

2.4.1. Capacitive Load of High-power SMBus Lines ........................................................... 27

2.4.2. Minimum Current Sinking Requirements for SMBus Devices.................................... 28

2.4.3. SMBus “Back Powering” Considerations ................................................................. 28

2.4.4. Power-on Reset .......................................................................................................... 28

2.5. JTAG PINS (OPTIONAL) ......................................................................................................... 29

2.6. AUXILIARY SIGNAL PARAMETRIC SPECIFICATIONS ................................................... 30

2.6.1. DC Specifications....................................................................................................... 30

2.6.2. AC Specifications ....................................................................................................... 31

3. HOT INSERTION AND REMOVAL..................................................................................33

3.1. SCOPE .................................................................................................................................... 33

3.2. PRESENCE DETECT................................................................................................................ 33

4. ELECTRICAL REQUIREMENTS .....................................................................................35

4.1. POWER SUPPLY REQUIREMENTS ...................................................................................... 35

4.2. POWER CONSUMPTION ........................................................................................................ 36

4.3. POWER SUPPLY SEQUENCING............................................................................................ 37

4.4. POWER SUPPLY DECOUPLING............................................................................................ 38

4.5. ELECTRICAL TOPOLOGIES AND LINK DEFINITIONS .................................................... 38

4.5.1. Topologies .................................................................................................................. 38

4.5.2. Link Definition............................................................................................................ 40

4.6. ELECTRICAL BUDGETS ........................................................................................................ 41

4.6.1. AC Coupling Capacitors ............................................................................................ 42

4.6.2. Insertion Loss Values (Voltage Transfer Function) ................................................... 42

4.6.3. Jitter Values................................................................................................................ 44

4.6.4. Crosstalk..................................................................................................................... 46

4.6.5. Lane-to-Lane Skew..................................................................................................... 46

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1

4.6.6. Equalization ............................................................................................................... 47

4.6.7. Skew within the Differential Pair ............................................................................... 47

4.7. EYE DIAGRAMS AT THE ADD-IN CARD INTERFACE..................................................... 47

4.7.1. Add-in Card Transmitter Path Compliance Eye-Diagram ........................................ 48

4.7.2. Add-in Card Minimum Receiver Path Sensitivity Requirements................................ 49

4.7.3. System Board Transmitter Path Compliance Eye Diagram....................................... 50

4.7.4. System Board Minimum Receiver Path Sensitivity Requirements.............................. 52

5. CONNECTOR SPECIFICATION.......................................................................................53

5.1. CONNECTOR PINOUT ............................................................................................................ 53

5.2. CONNECTOR INTERFACE DEFINITIONS ........................................................................... 58

5.3. SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES ................................ 62

5.4. CONNECTOR ENVIRONMENTAL AND OTHER REQUIREMENTS ................................ 65

5.4.1. Environmental Requirements ..................................................................................... 65

5.4.2. Mechanical Requirements .......................................................................................... 67

5.4.3. Current Rating Requirement ...................................................................................... 68

5.4.4. Additional Considerations.......................................................................................... 69

6. ADD-IN CARD FORM FACTORS AND IMPLEMENTATION ....................................71

6.1. ADD-IN CARD FORM FACTORS........................................................................................... 71

6.2. CONNECTOR AND ADD-IN CARD LOCATIONS ............................................................... 81

6.3. CARD INTEROPERABILITY .................................................................................................. 87

ACKNOWLEDGEMENTS ........................................................................................................89

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV. 1.1

Figures

FIGURE 1-1: VERTICAL EDGE-CARD CONNECTOR ................................................................. 11

FIGURE 1-2: EXAMPLE SERVER I/O BOARD WITH PCI EXPRESS SLOTS ON A RISER ..... 12

FIGURE 2-1: DIFFERENTIAL REFCLK WAVEFORM ................................................................. 14

FIGURE 2-2: EXAMPLE REFERENCE CLOCK SOURCE TERMINATION................................ 15

FIGURE 2-3: SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT

AND SWING ............................................................................................................................. 17

FIGURE 2-4: SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT.......... 17

FIGURE 2-5: SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME

MATCHING............................................................................................................................... 18

FIGURE 2-6: DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD 18

FIGURE 2-7: DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME .......... 18

FIGURE 2-8: DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK ............................. 18

FIGURE 2-9: REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING ....... 19

FIGURE 2-10: POWER UP ................................................................................................................ 21

FIGURE 2-11: POWER MANAGEMENT STATES......................................................................... 22

FIGURE 2-12: OUT-OF-TOLERANCE THRESHOLD WINDOWS ............................................... 23

FIGURE 2-13: POWER DOWN......................................................................................................... 23

FIGURE 2-14: WAKE# RISE AND FALL TIME MEASUREMENT POINTS............................... 31

FIGURE 3-1: PRESENCE DETECT IN A HOT-PLUG ENVIRONMENT...................................... 34

FIGURE 4-1: PCI EXPRESS ON THE SYSTEM BOARD............................................................... 39

FIGURE 4-2: PCI EXPRESS CONNECTOR ON SYSTEM BOARD WITH AN ADD-IN CARD. 39

FIGURE 4-3: PCI EXPRESS CONNECTOR ON A RISER CARD WITH AN ADD-IN CARD .... 40

FIGURE 4-4: LINK DEFINITION FOR TWO COMPONENTS ...................................................... 41

FIGURE 4-5: EXAMPLE INTERCONNECT TERMINATED AT THE CONNECTOR

INTERFACE .............................................................................................................................. 42

FIGURE 4-6: INSERTION LOSS BUDGETS ................................................................................... 43

FIGURE 4-7: JITTER BUDGET ........................................................................................................ 44

FIGURE 4-8: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE DIAGRAM............ 48

FIGURE 4-9: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR ADD-IN CARD

RECEIVER PATH COMPLIANCE .......................................................................................... 49

FIGURE 4-10: SYSTEM BOARD TRANSMITTER PATH COMPOSITE COMPLIANCE EYE

DIAGRAM ................................................................................................................................. 50

FIGURE 4-11: TWO-PORT MEASUREMENT MODEL ................................................................. 51

FIGURE 4-12: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR SYSTEM BOARD

RECEIVER PATH COMPLIANCE .......................................................................................... 52

FIGURE 5-1: CONNECTOR FORM FACTOR................................................................................. 58

FIGURE 5-2: RECOMMENDED FOOTPRINT ................................................................................ 59

FIGURE 5-3: ADD-IN CARD EDGE-FINGER DIMENSIONS ....................................................... 60

FIGURE 5-4: ILLUSTRATION OF ADJACENT PAIRS ................................................................. 65

FIGURE 5-5: CONTACT RESISTANCE MEASUREMENT POINTS............................................ 66

FIGURE 6-1: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITHOUT THE I/O

BRACKET ................................................................................................................................. 72

FIGURE 6-2: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET

AND CARD RETAINER........................................................................................................... 73

FIGURE 6-3: ADDITIONAL FEATURE AND KEEPOUTS ON THE X16 GRAPHICS CARD ... 74

FIGURE 6-4: STANDARD ADD-IN CARD I/O BRACKET ........................................................... 75

FIGURE 6-5: BRACKET DESIGN WITH THE MOUNTING TABS MOUNTED ON THE

PRIMARY SIDE OF THE ADD-IN CARD .............................................................................. 76

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laoer7

2014-05-30

很好，找很久了！
curious_cat

2012-02-08

找了好久了，完整名称为《PCI Express Card Electromechanical Specification Revision 1.1》；里面包含了PCIe 卡的热插拔、电气特性、连接器、机械尺寸的要求，对设计PCI EXPREE卡有重要的帮助作用。
arnoldm

2013-05-09

不错，原版的