Virtex-5 FPGA User Guide www.xilinx.com UG190 (v5.3) May 17, 2010
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Revision History
The following table shows the revision history for this document.
Date Version Revision
04/14/06 1.0 Initial Xilinx release.
05/12/06 1.1 Minor typographical edits and clarifications.
Chapter 1: Revised Figure 1-21.
Chapter 2: Revised Figure 2-2 and Figure 2-4. Removed reference to a DCM_PS
primitive. Removed outdated clocking wizard section page 83.
Chapter 3: Revised Figure 3-1, Figure 3-2, Table 3-2, Table 3-4, Figure 3-9, Equation 3-8,
and Figure 3-12. Added PLL in Virtex-4 FPGA PMCD Legacy Mode section.
Chapter 4: Added a note to Table 4-5, page 124. Clarified the RAMB36 port mapping
design rules on page 132.
Chapter 5: Added Figure 5-7 and Figure 5-11, revised Figure 5-32 for clarity.
Chapter 6: Updated Simultaneous Switching Output Limits section.
Chapter 7: Revised ILOGIC Resources, page 318 including Figure 7-1. Revised Table 7-3.
Chapter 8: Revised Table 8-1.
7/19/06 1.2 Chapter 1: Revised Global Clock Buffers, page 27 to clarify single-ended clock pins.
Changed the P and N I/O designations in Figure 1-19.
Chapter 4: Added Block RAM SSR in Register Mode, page 133 and FIFO Architecture: a
Top-Level View, page 142. Revised the FIFO operations Reset, page 144 description.
Chapter 6: Minor clarification edits. Changed to N/A from unused in Table 6-36,
Table 6-37, and Table 6-38.
Chapter 7: Minor edits to clarify IODELAY in this chapter.
Chapter 8: Small clarifications in ISERDES_NODELAY Ports, page 355.
i君莫笑2012-05-31这个可以到官网上去下，而且没技术含量，可以翻译一下
