JEDEC Standard No. 79-4D
Contents
i
1. Scope ............................................................................................................................................................. 1
2. DDR4 SDRAM Package Pinout and Addressing............................................................................................ 1
2.1 DDR4 SDRAM Row for X4, X8 and X16.................................................................................................... 1
2.2 DDR4 SDRAM Ball Pitch ........................................................................................................................... 1
2.3 DDR4 SDRAM Columns for X4, X8, and X16............................................................................................ 1
2.4 DDR4 SDRAM X4/8 Ballout using MO-207 ............................................................................................... 2
2.5 DDR4 SDRAM X16 Ballout using MO-207 ................................................................................................ 3
2.6 DDR4 SDRAM X32 Ballout using MO-XXX ............................................................................................... 4
2.7 Pinout Description...................................................................................................................................... 5
2.8 DDR4 SDRAM Addressing ........................................................................................................................ 7
2.9 DDP Single Rank (SR) x16 from two x8 .................................................................................................... 8
3. Functional Description .................................................................................................................................... 10
3.1 Simplified State Diagram ........................................................................................................................... 10
3.2 Basic Functionality ..................................................................................................................................... 11
3.3 RESET and Initialization Procedure........................................................................................................... 11
3.3.1 Power-up Initialization Sequence................................................................................................... 11
3.3.2 VDD Slew rate at Power-up Initialization Sequence ...................................................................... 14
3.3.3 Reset Initialization with Stable Power ............................................................................................ 14
3.4 Register Definition...................................................................................................................................... 15
3.4.1 Programming the mode registers .................................................................................................. 15
3.5 Mode Register............................................................................................................................................ 18
4. DDR4 SDRAM Command Description and Operation.................................................................................... 29
4.1 Command Truth Table................................................................................................................................ 29
4.2 CKE Truth Table......................................................................................................................................... 30
4.3 Burst Length, Type and Order.................................................................................................................... 31
4.3.1 BL8 Burst order with CRC Enabled................................................................................................ 31
4.4 DLL-off Mode & DLL on/off Switching procedure....................................................................................... 32
4.4.1 DLL on/off switching procedure...................................................................................................... 32
4.4.2 DLL “on” to DLL “off” Procedure .................................................................................................... 32
4.4.3 DLL “off” to DLL “on” Procedure .................................................................................................... 33
4.5 DLL-off Mode ............................................................................................................................................. 34
4.6 Input Clock Frequency Change ................................................................................................................. 35
4.7 Write Leveling ............................................................................................................................................ 36
4.7.1 DRAM setting for write leveling & DRAM termination function in that mode ................................. 37
4.7.2 Procedure Description ................................................................................................................... 38
4.7.3 Write Leveling Mode Exit ............................................................................................................... 39
4.8 Temperature Controlled Refresh modes .................................................................................................... 39
4.8.1 Normal Temperature Mode (TCASE not exceed 85°C) ................................................................ 39
4.8.2 Extended Temperature Mode (TCASE not exceed 95°C) ............................................................. 39
4.9 Fine Granularity Refresh Mode.................................................................................................................. 40
4.9.1 Mode Register and Command Truth Table ................................................................................... 40
4.9.2 tREFI and tRFC parameters .......................................................................................................... 40
4.9.3 Changing Refresh Rate ................................................................................................................. 41
4.9.4 Usage with Temperature Controlled Refresh mode ...................................................................... 42
4.9.5 Self Refresh entry and exit ............................................................................................................ 43
4.10 Multi Purpose Register............................................................................................................................. 43
4.10.1 DQ Training with MPR ................................................................................................................. 43
4.10.2 MR3 definition ............................................................................................................................. 43
4.10.3 MPR Reads ................................................................................................................................. 44
4.10.4 MPR Writes ................................................................................................................................. 46
4.10.5 MPR Read Data format ............................................................................................................... 49
4.11 Data Mask(DM), Data Bus Inversion (DBI) and TDQS ............................................................................ 54
4.12 ZQ Calibration Commands ...................................................................................................................... 56
4.12.1 ZQ Calibration Description .......................................................................................................... 56
4.13 DQ Vref Training ...................................................................................................................................... 57
4.13.1 Example scripts for VREFDQ Calibration Mode: ......................................................................... 60
4.14 Per DRAM Addressability......................................................................................................................... 63
4.15 CAL Mode (CS_n to Command Address Latency)................................................................................... 66
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