《开源指令集RISC-V手册》May31,2016资源-CSDN下载

RISC-V

需积分: 49 27 浏览量 2016-11-13 21:16:56 上传评论 4 收藏 598KB PDF 举报

资源推荐

资源详情

资源评论

The RISC-V Instruction Set Manual

Volume I: User-Level ISA

Version 2.1

Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanovi´c

CS Division, EECS Department, University of California, Berkeley

{waterman|yunsup|pattrsn|krste}@eecs.berkeley.edu

May 31, 2016

This document is also available as Technical Report UCB/EECS-2016-118.

Preface

This is version 2.1 of the document describing the RISC-V user-level architecture. Note the frozen

user-level ISA base and extensions IMAFDQ version 2.0 have not changed from the previous version

of this document [30], but some speciﬁcation holes have been ﬁxed and the documentation has been

improved. Some changes have been made to the software conventions.

• Numerous additions and improvements to the commentary sections.

• Separate version numbers for each chapter.

• Modiﬁcation to long instruction encodings >64 bits to avoid moving the rd speciﬁer in very

long instruction formats.

• CSR instructions are now described in the base integer format where the counter registers

are introduced, as opposed to only being introduced later in the ﬂoating-point section (and

the companion privileged architecture manual).

• The SCALL and SBREAK instructions have been renamed to ECALL and EBREAK, re-

spectively. Their encoding and functionality are unchanged.

• Clariﬁcation of ﬂoating-point NaN handling, and a new canonical NaN value.

• Clariﬁcation of values returned by ﬂoating-point to integer conversions that overﬂow.

• Clariﬁcation of LR/SC allowed successes and required failures, including use of compressed

instructions in the sequence.

• A new RV32E base ISA proposal for reduced integer register counts.

• A revised calling convention.

• Relaxed stack alignment for soft-ﬂoat calling convention, and description of the RV32E calling

convention.

• A revised proposal for the C compressed extension, version 1.9.

Preface to Version 2.0

This is the second release of the user ISA speciﬁcation, and we intend the speciﬁcation of the

base user ISA plus general extensions (i.e., IMAFD) to remain ﬁxed for future development. The

following changes have been made since Version 1.0 [29] of this ISA speciﬁcation.

• The ISA has been divided into an integer base with several standard extensions.

• The instruction formats have been rearranged to make immediate encoding more eﬃcient.

• The base ISA has been deﬁned to have a little-endian memory system, with big-endian or

bi-endian as non-standard variants.

ii Volume I: RISC-V User-Level ISA V2.1

• Load-Reserved/Store-Conditional (LR/SC) instructions have been added in the atomic in-

struction extension.

• AMOs and LR/SC can support the release consistency model.

• The FENCE instruction provides ﬁner-grain memory and I/O orderings.

• An AMO for fetch-and-XOR (AMOXOR) has been added, and the encoding for AMOSWAP

has been changed to make room.

• The AUIPC instruction, which adds a 20-bit upper immediate to the PC, replaces the RDNPC

instruction, which only read the current PC value. This results in signiﬁcant savings for

position-independent code.

• The JAL instruction has now moved to the U-Type format with an explicit destination

removes the only instruction with an implicit destination register and removes the J-Type

instruction format from the base ISA. There is an accompanying reduction in JAL reach, but

a signiﬁcant reduction in base ISA complexity.

• The static hints on the JALR instruction have been dropped. The hints are redundant with

the rd and rs1 register speciﬁers for code compliant with the standard calling convention.

• The JALR instruction now clears the lowest bit of the calculated target address, to simplify

hardware and to allow auxiliary information to be stored in function pointers.

• The MFTX.S and MFTX.D instructions have been renamed to FMV.X.S and FMV.X.D,

respectively. Similarly, MXTF.S and MXTF.D instructions have been renamed to FMV.S.X

and FMV.D.X, respectively.

• The MFFSR and MTFSR instructions have been renamed to FRCSR and FSCSR, respec-

tively. FRRM, FSRM, FRFLAGS, and FSFLAGS instructions have been added to individu-

ally access the rounding mode and exception ﬂags subﬁelds of the fcsr.

• The FMV.X.S and FMV.X.D instructions now source their operands from rs1, instead of rs2.

This change simpliﬁes datapath design.

• FCLASS.S and FCLASS.D ﬂoating-point classify instructions have been added.

• A simpler NaN generation and propagation scheme has been adopted.

• For RV32I, the system performance counters have been extended to 64-bits wide, with separate

read access to the upper and lower 32 bits.

• Canonical NOP and MV encodings have been deﬁned.

• Standard instruction-length encodings have been deﬁned for 48-bit, 64-bit, and >64-bit in-

structions.

• Description of a 128-bit address space variant, RV128, has been added.

• Major opcodes in the 32-bit base instruction format have been allocated for user-deﬁned

custom extensions.

• A typographical error that suggested that stores source their data from rd has been corrected

to refer to rs2.

剩余130页未读，继续阅读

评论收藏

内容反馈

sugar_028

粉丝: 1

《开源指令集RISC-V手册》May 31, 2016

最新资源

《开源指令集RISC-V手册》May 31, 2016

RISC-V指令集手册

RISC-V 中文教程手册

riscv-isa-manual:RISC-V指令集手册

RISC-V指令集中文.zip

RISC-V中文架构手册

RISC-V 指令集手册

RISC-V中文手册，汇编指令集手册

RISC-V指令集手册卷1.pdf

risc-v指令集、中文手册

RISC-V中文手册.pdf

RISC-V中文架构手册开源指令集的指南 RISC-V-Reader-Chinese-v2p1

RISC-V-Reader-Chinese-v2p1_risc-v_RISC-V开源MCU指令集手册_源码.zip

RISC-V-Reader-Chinese-v2p1_risc-v_RISC-V开源MCU指令集手册

RISC-V 中文版手册

Open risc学习材料

RISC-V-手册1

risc-v指令集详解

RISC-V 指令集手册-v2.1中文版.pdf

RISC-V官方手册和相关资料（特权架构 & 非特权架构 & 中文资料）

RISC-V-Reference-Data指令卡片-考试版1

RISC-V手册-中文版.rar_Risc v 手册_risc_risc v_risc-v中文手册_risc_v

RISC-V手册.zip

riscv-card指令集手册

riscv-spec中文版

RISC-V 压缩指令集手册 中文版

RISCV中文架构手册

一维数组和二维数组

白名单合同：用AssemblyScript编写的白名单合同（NEAR核心合同）

最新资源

RISC-V 压缩指令集手册中文版