
Section number Title Page
1.2.8.3 e6500/SC3900FP FVP MMU and embedded Hypervisor.......................................................107
1.2.8.4 Peripheral access management unit (PAMU).......................................................................... 108
1.2.8.5 Integrated Flash Controller (IFC)............................................................................................ 108
1.2.9 OCeaN DMA............................................................................................................................................... 109
1.2.10 High-speed peripheral interface complex.................................................................................................... 109
1.2.10.1 Ethernet.................................................................................................................................... 110
1.2.10.2 Serial RapidIO..........................................................................................................................110
1.2.10.3 PCI Express controller............................................................................................................. 110
1.2.10.4 Common Public Radio Interface (CPRI) controller.................................................................111
1.2.10.5 Debug (Aurora) support...........................................................................................................113
1.2.11 System peripherals....................................................................................................................................... 113
1.2.11.1 Universal Serial Bus (USB) 2.0............................................................................................... 113
1.2.11.2 Enhanced Serial Peripheral Interface (eSPI)............................................................................114
1.2.11.3 Dual UART (DUART).............................................................................................................114
1.2.11.4 Enhanced SD Host Controller (eSDHC)..................................................................................115
1.2.11.5 Timers...................................................................................................................................... 115
1.2.11.6 I2C interface.............................................................................................................................116
1.2.11.7 General-Purpose Input/Output (GPIO) ports........................................................................... 116
1.2.11.8 Boot interface...........................................................................................................................116
1.2.11.9 JTAG........................................................................................................................................117
1.2.12 Trust architecture......................................................................................................................................... 117
1.2.12.1 Secure boot and sensitive data protection................................................................................117
1.2.12.1.1 Secure boot option............................................................................................ 118
1.2.12.1.2 Sensitive data protection option........................................................................118
1.2.13 Clocking.......................................................................................................................................................118
1.2.14 Advanced power management.....................................................................................................................118
1.2.15 Debug support..............................................................................................................................................119
B4860 QorIQ Qonverge Multicore Baseband Processor Reference Manual, Rev. J, 07/2014
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Preliminary
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