基于UVM的AHB总线SRAM控制器设计验证平台设计

共37个文件

sv：24个

v：6个

png：5个

数字IC

数字IC验证

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UVM_AHB_SRAMC_CONTROL.zip （37个子文件）

RTL

sram_core.v 13KB

sram_bist_8kx8.v 14KB

ahb_slave_if.v 15KB

sram_bist.v 5KB

sramc_top.v 6KB

RA1SH.v 12KB

hszie32.png 230KB

tb_sramc_top.sv 5KB

hsize8.png 259KB

bankn_csn.png 600KB

ahb_wr_rd_ctr.jpg 55KB

README.md 5KB

ahb_sramc_control_architecture.png 516KB

UVM

my_virtual_sequencer.sv 416B

my_model.sv 1KB

my_env.sv 2KB

base_test.sv 1KB

tb_top.sv 7KB

read_sramc_sequencer.sv 349B

my_scoreboard.sv 2KB

my_case2.sv 2KB

read_sramc_agent.sv 1KB

write_sramc_seq.sv 847B

my_transaction.sv 378B

write_sramc_sequencer.sv 348B

write_sramc_driver.sv 3KB

my_case1.sv 2KB

define.sv 714B

read_sramc_seq.sv 840B

write_sramc_monitor.sv 1KB

my_if.sv 2KB

write_sramc_agent.sv 1KB

read_sramc_monitor.sv 1KB

read_sramc_driver.sv 3KB

read_sramc_transaction.sv 402B

my_case0.sv 2KB

hsize16.png 242KB

# UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design ## ahb_sramc_control_architecture ![ahb_sramc_control_architecture](https://user-images.githubusercontent.com/71707557/184055306-04816a4b-d1ee-4d11-9e7d-ba9e5cb4407a.png) UVM testbench topology ------------------------------------------------------------------ Name Type Size Value uvm_test_top my_case1 - @457 env my_env - @473 agt_mdl_fifo uvm_tlm_analysis_fifo #(T) - @693 analysis_export uvm_analysis_imp - @737 get_ap uvm_analysis_port - @728 get_peek_export uvm_get_peek_imp - @710 put_ap uvm_analysis_port - @719 put_export uvm_put_imp - @701 agt_scb_fifo uvm_tlm_analysis_fifo #(T) - @640 analysis_export uvm_analysis_imp - @684 get_ap uvm_analysis_port - @675 get_peek_export uvm_get_peek_imp - @657 put_ap uvm_analysis_port - @666 put_export uvm_put_imp - @648 i_agt write_sramc_agent - @485 drv write_sramc_driver - @926 rsp_port uvm_analysis_port - @943 seq_item_port uvm_seq_item_pull_port - @934 mon write_sramc_monitor - @952 ap uvm_analysis_port - @962 sqr write_sramc_sequencer - @803 rsp_export uvm_analysis_export - @811 seq_item_export uvm_seq_item_pull_imp - @917 arbitration_queue array 0 - lock_queue array 0 - num_last_reqs integral 32 'd1 num_last_rsps integral 32 'd1 m_vseqr my_virtual_sequencer - @517 rsp_export uvm_analysis_export - @525 seq_item_export uvm_seq_item_pull_imp - @631 arbitration_queue array 0 - lock_queue array 0 - num_last_reqs integral 32 'd1 num_last_rsps integral 32 'd1 mdl my_model - @501 ap uvm_analysis_port - @990 port uvm_blocking_get_port - @981 mdl_scb_fifo uvm_tlm_analysis_fifo #(T) - @746 analysis_export uvm_analysis_imp - @790 get_ap uvm_analysis_port - @781 get_peek_export uvm_get_peek_imp - @763 put_ap uvm_analysis_port - @772 put_export uvm_put_imp - @754 o_agt read_sramc_agent - @493 drv read_sramc_driver - @1134 rsp_port uvm_analysis_port - @1151 seq_item_port uvm_seq_item_pull_port - @1142 mon read_sramc_monitor - @1126 ap uvm_analysis_port - @1162 sqr read_sramc_sequencer - @1003 rsp_export uvm_analysis_export - @1011 seq_item_export uvm_seq_item_pull_imp - @1117 arbitration_queue array 0 - lock_queue array 0 - num_last_reqs integral 32 'd1 num_last_rsps integral 32 'd1 scb my_scoreboard - @509 act_port uvm_blocking_get_port - @1185 exp_port uvm_blocking_get_port - @1176 ------------------------------------------------------------------

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