Fairness-Oriented Switch Allocation for
Networks-on-Chip
Zicong Wang
∗
, Xiaowen Chen
∗†
, Chen Li
∗
and Yang Guo
∗
∗
College of Computer, National University of Defense Technology, Changsha, Hunan, China
†
Department of Electronics, KTH Royal Institute of Technology, Kista, Stockholm, Sweden
Email: {wangzicong,xwchen,lichen,guoyang}@nudt.edu.cn
Abstract—Networks-on-Chip (NoC) is becoming the backbone
of modern chip multiprocessor (CMP) systems. However, with
the number of integrated cores increasing and the network
size scaling up, the network-latency imbalance is becoming an
important problem, which seriously influences the performance
of the network and system. In this paper, we aim to alleviate
this problem by optimizing the design of switch allocation.
We propose fairness-oriented switch allocation (FOSA), a novel
switch allocation strategy to achieve uniform network latencies.
FOSA can improve system performance by achieving remarkable
improvement in balancing network latencies. We evaluate the
network and system performance of FOSA with synthetic traffics
and SPEC CPU2006 benchmarks in a full-system simulator.
Compared with the canonical separable switch allocator (Round-
Robin) and the recently proposed switch allocator (TS-Router),
the experiments with benchmarks show that our approach de-
creases maximum latency (ML) by 45.6% and 15.1%, respectively,
as well as latency standard deviation (LSD) by 13.8% and 3.9%,
respectively. Besides this, FOSA improves system throughput by
0.8% over that of TS-Router. Finally, we synthesize FOSA and
give an evaluation of the additional consumption of area and
power.
I. INTRODUCTION
As the number of cores integrated on chip multiproces-
sors (CMP) continues to increase, Networks-on-Chip (NoC)
is gradually becoming the best solution for interconnection.
However, as the network size scales up, the communication
distance and latency between cores increase, and NoC can
considerably affect system performance. Therefore, NoC effi-
ciency is important for improving system performance.
Many prior research projects make a great effort to design
an efficient router to meet the demands of communication
between cores [1]–[5]. However, an important but easily over-
looked problem affecting performance is the network-latency
imbalance, which refers to the non-uniform latencies in net-
work communication. A larger latency gap implies more net-
work packets suffering from higher latencies, which become
the bottleneck of the system and worsen the performance.
There are two reasons for the network-latency imbalance
problem. Firstly, take the two-dimensional mesh network as
an example. As the cores reside in different locations (center
or periphery), the cores located in the center have an advantage
over others in terms of communication. Specifically, the central
work is supported by the National Natural Science Foundation of China (No.
61502508 and No. 61402499) and the Hunan Natural Science Foundation of
China (No. 2015JJ3017).
cores are closer to others on average, compared with peripheral
cores. The average communication distance gap between cores
becomes even larger with the scaling up of network size.
Secondly, inappropriate packet (flit) scheduling strategy and
anti-starvation criterion in router design can exacerbate the
network-latency imbalance problem, since the majority of
strategies overly concentrate on improving the efficiency of
scheduling and rarely address this problem.
To achieve more balanced network latencies, the composi-
tion of network latency is analyzed first. In the absence of
contention, the packet latency (i.e., the zero-load latency) can
be determined by the following expression [6]:
T
0
= H × (t
r
+ t
l
) +
L
b
(1)
H indicates the hop count of the packet traveling from the
source node to the destination node. t
r
and t
l
, respectively,
denote the delay through a single router and a single link.
L/b stands for the time for the packet with length L to cross
a link with bandwidth b (i.e., the serialization delay). If we
take the contention into consideration, we can introduce t
w
to Equation 1, which reflects the average waiting time for a
single switch, as follows:
T = H × (t
r
+ t
l
+ t
w
) +
L
b
(2)
Note that t
r
, t
l
, and b are constant under determined network
parameters and router architecture. Furthermore, H and L are
also determined for a specific packet (assuming deterministic
routing is applied). In contrast, the t
w
for a specific packet
can vary considerably with the switch allocation strategy,
which probably results in some packets suffering from high
latencies. Therefore, our work focuses on regulating t
w
in
switch allocation.
In this paper, we aim to alleviate the network-latency
imbalance problem by reconsidering the objective of switch
allocation. Different from most traditional efficiency-oriented
switch allocators, we propose fairness-oriented switch allo-
cation (FOSA), a novel switch allocation strategy that takes
fairness as the primary objective to achieve more balanced
network latencies. Our approach uses fairness to denote the
degree of network-latency equalization, which is measured
by the metrics of latency standard deviation (LSD) and
maximum latency (ML). The basic idea of our approach is
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