caideng.rar_LED 控制器_caideng

--SXKZ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SXKZ IS PORT(CHOSE_KEY:IN STD_LOGIC; CLK_IN:IN STD_LOGIC; CLR:IN STD_LOGIC; CLK:OUT STD_LOGIC); END ENTITY SXKZ; ARCHITECTURE ART OF SXKZ IS SIGNAL CLLK:STD_LOGIC; BEGIN PROCESS(CLK_IN,CLR,CHOSE_KEY) IS VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN IF CLR='1' THEN --当CLR='1'时清零，否则正常工作 CLLK<='0';TEMP:="000"; ELSIF RISING_EDGE(CLK_IN) THEN IF CHOSE_KEY='1' THEN IF TEMP="011" THEN TEMP:="000"; CLLK<=NOT CLLK ; ELSE TEMP:=TEMP+'1'; END IF; -- 当CHOSE_KEY='1'时产生基准时钟频率的1/4的时钟信号，否则产生基准时钟 --频率的1/8的时钟信号 ELSE IF TEMP="111" THEN TEMP:="000"; CLLK<=NOT CLLK ; ELSE TEMP:=TEMP+'1'; END IF; END IF; END IF; END PROCESS; CLK<=CLLK; END ARCHITECTURE ART; 显示控制电路的VHDL源程序 --XSKZ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY XSKZ IS PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; LED:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ENTITY XSKZ; ARCHITECTURE ART OF XSKZ IS TYPE STATE IS(S0,S1,S2,S2,S4,S5,S6); SIGNAL CURRENT_STATE:STATE; SIGNAL FLOWER:STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN PROCESS(CLR,CLK) IS CONSTANT F1:STD_LOGIC_VECTOR(15 DOWNTO 0):="0001000100010001"; CONSTANT F2:STD_LOGIC_VECTOR(15 DOWNTO 0):="1010101010101010"; CONSTANT F2:STD_LOGIC_VECTOR(15 DOWNTO 0):="0011001100110011"; CONSTANT F4:STD_LOGIC_VECTOR(15 DOWNTO 0):="0100100100100100"; CONSTANT F5:STD_LOGIC_VECTOR(15 DOWNTO 0):="1001010010100101"; CONSTANT F6:STD_LOGIC_VECTOR(15 DOWNTO 0):="1101101101100110"; --六种花型的定义 BEGIN IF CLR='1' THEN CURRENT_STATE<=S0; ELSIF RISING_EDGE(CLK) THEN CASE CURRENT_STATE IS WHEN S0=> FLOWER<="ZZZZZZZZZZZZZZZZ"; CURRENT_STATE<=S1; WHEN S1=> FLOWER<=F1; CURRENT_STATE<=S2; WHEN S2=> FLOWER<=F2; CURRENT_STATE<=S2; WHEN S2=> FLOWER<=F2; CURRENT_STATE<=S4; WHEN S4=> FLOWER<=F4; CURRENT_STATE<=S5; WHEN S5=> FLOWER<=F5; CURRENT_STATE<=S6; WHEN S6=> FLOWER<=F6; CURRENT_STATE<=S1; END CASE; END IF; END PROCESS; LED<=FLOWER; END ARCHITECTURE ART; 整个电路系统的VHDL源程序 --CDKZQ.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY CDKZQ IS PORT(CLK_IN:IN STD_LOGIC; CLR:IN STD_LOGIC; CHOSE_KEY:IN STD_LOGIC; LED:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END ENTITY CDKZQ; ARCHITECTURE ART OF CDKZQ IS COMPONENT SXKZ IS PORT(CHOSE_KEY:IN STD_LOGIC; CLK_IN:IN STD_LOGIC; CLR:IN STD_LOGIC; CLK:OUT STD_LOGIC); END COMPONENT SXKZ; COMPONENT XSKZ IS PORT(CLK:IN STD_LOGIC; CLR:IN STD_LOGIC; LED:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END COMPONENT XSKZ; SIGNAL S1:STD_LOGIC; BEGIN U1:SXKZ PORT MAP(CHOSE_KEY,CLK_IN,CLR,S1); U2:XSKZ PORT MAP(S1,CLR,LED); END ARCHITECTURE ART;