FIFO.rar_Cy68013 usb固件_cypress fifo

This directory contains 8051 firmware for the Cypress Semiconductor EZ-USB FX2 chip. The purpose of this code is to demonstrate how to utilize EZUSB FX2 Slave FIFOs Programmable Flag interrupt (via core INT4 Autovector). It configures FX2 as follows: 01). EP2 512 2x BULK OUT - 8-bit async AUTO mode 02). EP4 512 2x BULK OUT - 8-bit async AUTO mode 03). EP6 512 2x BULK OUT - 8-bit async AUTO mode 04). EP8 512 2x BULK OUT - 8-bit async AUTO mode 05). FIFO strobes and flags are all active low 06). FLAGA/B/C - indexed via FIFOADR[1:0] pins .....from the ext. master (in this case is FX2 in GPIF mode or manual jumpers for FIFOADR[1:0] pins configuration ) 01). External master points to EP2, as outlined below: 02). External master points to EP4, as outlined below: 03). External master points to EP6, as outlined below: 04). External master points to EP8, as outlined below: .....from "the user": 01). Initially strap: - FIFOADR[1:0=00 02). Setup Logic Analyzer to trigger on FLAGA(PF) both leading and trailing edge(s) 03). Download "edgepf.hex" via EZUSB Control Panel - note: the four debug LED[3:0]s are ON... 04). Issue "Get String" 05). Issue "Get Pipes" 06). Issue "Get Conf" 07). Issue "Get Dev" 08). Issue 0xB2 VendReg 64 IN - this should clear all four debug LED[3:0]s 09). Issue 0xC7 VendReg 64 IN - this puts the part in AUTOOUT mode (a must for this example) 10). Trigger Logic Analyzer on FLAGA(PF) 11). BulkTrans EP2 OUT 512 data (or more if you wish) 12). Examine Logic Analyzer output - Logic Analyzer triggers on FLAGA - LED0 should be ON 13). Strap: - FIFOADR[1:0=01 14). Trigger Logic Analyzer on FLAGA(PF) 15). BulkTrans EP4 OUT 512 data (or more if you wish) 16). Examine Logic Analyzer output - Logic Analyzer triggers on FLAGA - LED[1:0] should be ON 17). Strap: - FIFOADR[1:0=10 18). Trigger Logic Analyzer on FLAGA(PF) 19). BulkTrans EP6 OUT 512 data (or more if you wish) 20). Examine Logic Analyzer output - Logic Analyzer triggers on FLAGA - LED[2:0] should be ON 21). Strap: - FIFOADR[1:0=11 22). Trigger Logic Analyzer on FLAGA(PF) 23). BulkTrans EP8 OUT 512 data (or more if you wish) 24). Examine Logic Analyzer output - Logic Analyzer triggers on FLAGA - LED[3:0] should be ON The "edgepf.hex" file loads into internal memory. ...issue "build -i" at the command prompt... This example is for illustrative purpose(s) and unless you have an ext. master that emulates the testing environment this example won't actually produce expected results when downloaded via Control Panel. The external master in this case is EZUSB FX2 running in GPIF master mode or could also be manual jumpers for the FIFOADR[1:0] pin configurations as described above...