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**MMX技术详解** MMX（MultiMedia eXtension），是英特尔公司在1996年推出的一种增强型指令集，旨在提升处理器处理多媒体数据的能力。这个技术的引入，为当时的计算机性能带来了显著的提升，特别是在图形处理和音频处理方面。MMX指令集通过增加新的寄存器和特定的指令，使得处理器能够并行处理多个数据元素，从而提高了运算效率。 **MMX指令集** MMX指令集包含了57条新的SIMD（单指令多数据）指令，这些指令允许处理器一次处理多个数据位宽的操作，如64位的整数或者四个32位的浮点数。MMX指令集主要针对整数运算优化，不涉及浮点计算，但可以用于图像处理、声音编码解码等多媒体应用。 **MMX寄存器** MMX技术引入了6个64位的MMX寄存器（MM0-MM5），它们可以被分割为两个32位部分，或者四个16位部分，甚至八个8位部分，以适应不同宽度的数据处理。这些寄存器可以同时存储和操作多个数据，大大提高了数据处理的并行性。 **编程规范** 在编程中使用MMX技术，通常需要采用汇编语言进行低级操作，以充分利用其并行处理能力。然而，为了方便C++或C程序员，可以使用内联汇编或特殊的库函数来调用MMX指令。编程时需要注意以下几点： 1. **数据对齐**：由于MMX操作需要数据对齐，因此内存分配和数据存储时必须确保适当的对齐，否则可能会引发异常。 2. **冲突检测**：MMX指令可能与浮点运算冲突，因此在使用MMX前需保存浮点状态，并在完成后恢复。 3. **寄存器管理**：程序需要妥善管理和保存MMX寄存器，避免与其他系统资源发生冲突。 4. **优化技巧**：合理利用MMX指令的并行处理能力，例如通过数据打包和解包来最大化并行计算。 **应用场景** MMX技术在许多领域都有应用，如： 1. **图像处理**：例如图像缩放、旋转、色彩转换等操作。 2. **音频处理**：如音频编码解码，音效处理等。 3. **视频编解码**：在MPEG视频编码中，MMX可以提高编码速度。 4. **科学计算**：在需要大量整数运算的领域，MMX也能提供性能提升。 **文件列表解析** 压缩包中的文件“bigtitle.gif”和一系列以“30060”开头的gif文件可能是教程或演示文稿中的图片，它们可能展示了MMX技术的应用示例、操作流程或者指令集的视觉表示。总结来说，MMX技术是一种重要的处理器增强手段，它通过扩展指令集和新增寄存器，提升了多媒体处理的效率。开发者可以通过内嵌汇编或者库函数的方式，在C++和C语言中利用MMX进行高效的编程。了解和掌握MMX技术，对于开发高效能的多媒体应用具有重要意义。

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MMX.zip （34个子文件）

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<html> <head> <meta content="charset=gb2312"> </head> <style type="text/css">  </style> <body bgcolor="#000000" text="#DBCAAE" link="#DBCAAE" vlink="#DBCAAE" alink="#DBCAAE" topmargin="10" leftmargin="4"> <center> <a href="tppmsgs/msgs0.htm#1" tppabs="http://freemind.163.net/index.html"><img src="bigtitle.gif" tppabs="http://freemind.163.net/bigtitle.gif" width=505 height=92 border="0"></a> </center> <big>DATABASE</big> <table border="0" cellpadding="0" cellspacing="0" width="100%"><tr><td bgcolor="#CBBA9E" height="1"></td></tr><tr><td bgcolor="#FBEACE" height="1"></td></tr><tr><td bgcolor="#DBCAAE" height="1"></td></tr><tr><td bgcolor="#BBAA8E" height="1"></td></tr><tr><td bgcolor="#9B8A6E" height="1"></td></tr><tr><td bgcolor="#7B6A4E" height="1"></td></tr><tr><td bgcolor="#5B4A2E" height="1"></td></tr><tr><td bgcolor="#3B2A0E" height="1"></td></tr><tr><td height="10"></td></tr></table> <center> <big>INTEL 体系结构 MMX 技术程序员参考手册</big> Intel Architecture MMX Technology Programmer's Reference Manual </center> <table border="0" width="100%" border="0" cellpadding="2" cellspacing="0"><tr><td align="right"><a href="mmx.htm" tppabs="http://freemind.163.net/database/mmx/mmx.htm">返回</a></td></tr></table> <table border="0" width="100%"><tr><td bgcolor="#CBBA9E" height="2"></td></tr></table> <h3>Chapter 5 INTEL ARCHITECTURE MMX INSTRUCTION SET</h3> This chapter presents the Intel Architecture MMX instructions in alphabetical order, with a full description of each instruction. The IA MMX technology defines fifty-seven new instructions. The instructions are grouped into the following functional categories: <ul> <li>Arithmetic Instructions <li>Comparison Instructions <li>Conversion Instructions <li>Logical Instructions <li>Shift Instructions <li>Data Transfer Instructions <li>Empty MMX State (EMMS) Instruction </ul> Appendix A summarizes the MMX instructions grouped by categories of related functions. Appendix B provides instruction formats and encodings, and Appendix C provides an alphabetical list of instruction mnemonics, their source data types, encodings in hexadecimal, and format. Appendix D provides an Opcode Map of the MMX instructions. Many of the instructions have multiple variations depending on the data types they support. Each variation has a different suffix. For example the PADD instruction has three variations: PADDB, PADDW, and PADDD, where the letters B, W, and D represent byte, word, and doubleword. <H3><a name="5.1">5.1 INSTRUCTION SYNTAX</a></H3> Instructions vary by: <ul> <li>Data type: packed bytes, packed words, packed doublewords or quadwords <li>Signed - Unsigned numbers <li>Wraparound - Saturate arithmetic </ul> A typical MMX instruction has this syntax: <ul> <li>Prefix: P for Packed <li>Instruction operation: for example - ADD, CMP, or XOR <li>Suffix: --US for Unsigned Saturation --S for Signed saturation --B, W, D, Q for the data type: packed byte, packed word, packed doubleword, or quadword. </ul> Instructions that have different input and output data elements have two data-type suffixes. For example, the conversion instruction converts from one data type to another. It has two suffixes: one for the original data type and the second for the converted data type. This is an example of an instruction mnemonic syntax: <ul> PADDUSW (Packed Add Unsigned with Saturation for Word) P = Packed ADD = the instruction operation US = Unsigned Saturation W = Word </ul> <H3><a name="5.2">5.2 INSTRUCTION FORMAT</a></H3> The IA MMX instructions use the existing IA instruction format. All instructions, except the EMMS instruction, use the ModR/M format. All are preceded by the 0F prefix byte. For more details about the ModR/M format refer to Pentium® Processor Family Developer's Manual Volume 3, Section 25.2.1. For data-transfer instructions, the destination and source operands can reside in memory, integer registers, or MMX registers. For all other IA MMX instructions, the destination operands reside in MMX registers, and the source operands reside in memory, MMX registers, or immediate operands. All existing address modes are supported using the SIB (Scale Index Base) format. <H3><a name="5.3">5.3 NOTATIONAL CONVENTIONS</a></H3> The following conventions apply to all MMX instructions (except the EMMS instruction): <ul> <li>The instructions reference and operate on two operands: the source and destination operands. The right operand is the source and the left operand is the destination. The destination operand may also supply one of the inputs for the operation. The instruction overwrites the destination operand with the result. <li>When one of the operands is a memory location, the linear address corresponds to the address of the least significant byte of the referenced memory data. <li>The MMX instructions do not affect the condition flags. </ul> <H3><a name="5.4">5.4 HOW TO READ THE INSTRUCTION SET PAGES</a></H3> The following is an example of the format used for each MMX instruction description in this chapter: PSLL - Packed Shift Left Logical <center><table border="0" cellpadding="2" cellspacing="1" bgcolor="#EBDABE"> <TR><TD bgcolor="#000000" WIDTH=136>Opcode</TD><TD bgcolor="#000000" WIDTH=136>Instruction </TD><TD bgcolor="#000000" WIDTH=245>Description</TD> </TR> <TR><TD bgcolor="#000000" WIDTH=136>0F F1 /r</TD><TD bgcolor="#000000" WIDTH=136>PSLLW mm, mm/m64 </TD><TD bgcolor="#000000" WIDTH=245>Shift all words in MMX register to left by an amount specified in MMX register/memory, while shifting in zeros. </TD></TR> </table></center> The above table gives the instruction mnemonic and a brief description of the mnemonic. The columns content are explained below. <ul> Opcode Column The "Opcode" column provides the complete opcode produced for each form of the instruction. The codes are defined as hexadecimal bytes, in the same order in which they appear in memory. Definitions of entries other than hexadecimal bytes are as follows: <ul> <li type=disc>/digit: (digit is between 0 and 7) indicates that the ModR/M byte of the instruction uses only the r/m (register or memory) operand. The reg field contains the digit that provides a technology to the instruction's opcode. <li>/r: indicates that the ModR/M byte of the instruction contains both a register operand and an r/m operand. <li>ib: a 1-byte, immediate operand to the instruction that follows the opcode, ModR/M bytes, and scale-indexing bytes. The opcode determines if the operand is a signed value. </ul> Instruction Column The "Instruction" column contains the instruction syntax. The following is a list o

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