
Hi3798M V300 Brief Data Sheet
Copyright © HiSilicon Technologies Co., Ltd. 2017. All rights reserved.
Huawei Industrial Base, Bantian, Longgang District, Shenzhen, P. R. China
Postal Code: 518129 1 www.hisilicon.com
Issue: 00B01 Date: 2017-07-04
Key Specifications
High-Performance CPU
Quad-core 64-bit high-performance ARM Cortex A53
Integrated multimedia acceleration engine NEON
Hardware Java acceleration
Integrated hardware floating-point coprocessor
3D GPU
Integrated high-performance multi-core GPU Mali-450
OpenGL ES 2.0/1.1 and OpenVG 1.1
Memory Control Interfaces
DDR3/DDR3L/DDR4 interface, supporting maximum
32-bit data width
eMMC 5.0 flash interface
Asynchronous/Synchronous NAND flash interface
− SLC/MLC flash memory
− Maximum 64-bit ECC
Video Decoding (HiVXE 2.0 Processing Engine)
H.265/HEVC Main/Main 10 Profile@Level 5.1 high-tier,
supporting 4K x 2K@60 fps decoding
H.264/AVC Baseline Profile/Main Profile/High
Profile@Level 5.1; H.264/AVC MVC, supporting 4K x
2K@30 fps decoding
VP9 10-bit, supporting 1080p@60 fps decoding
1080p@60 fps decoding, supported by MPEG-1
MPEG-2 Simple Profile@Main Level, Main
Profile@High Level, supporting 1080p@60 fps decoding
MPEG-4 Simple Profile@Levels 0–3, ASP@Levels 0–5,
supporting GMC, short header format, and 1080p@60 fps
decoding
AVS-P16 (AVS+), supporting 1080p@60 fps decoding
Image Decoding
JPEG decoding, maximum 64 megapixels
PNG decoding, maximum 64 megapixels
Video and Image Encoding
H.265 MP@level 5 main tier and H.264
BP/MP/HP@level 4.2 video encoding, maximum
1x1080p@30 fps
VBR or CBR mode for video encoding
Low-delay encoding
Multi-ROI encoding
Audio Encoding and Decoding
MPEG L1/L2
Dolby Digital/Dolby Digital Plus decoder-converter
Dolby Digital/DTS passthrough
Dolby Atmos
AAC-LC and HE-AAC V1/V2 decoding
APE, FLAC, Ogg, AMR-NB, and AMR-WB decoding
G.711 (u/a) audio decoding
G.711 (u/a), AMR-NB, AMR-WB, and AAC-LC audio
encoding
HE-AAC transcoding DD (AC3)
Security Processing
Secure boot, secure storage, and secure upgrade
ChinaDRM
HDCP 2.2/1.4 for HDMI outputs
Graphics and Display Processing (Imprex 2.0
Processing Engine)
HDR10/HLG HDR/SLF HDR
Image enhancement algorithm
Conversion from HDR to SDR
Hardware overlaying of multi-channel graphics and video
inputs
Multiple graphics layers and video layers
Multi-order vertical and horizontal scaling of videos and
graphics; free scaling
Screen mirroring and video rotation
Full-format 3D video processing and display
Enhanced TDE
Anti-aliasing, anti-flicker, enhancement of image colors
and luminance, NR, DEI, sharpening, as well as
adjustment of the luminance, chrominance, contrast, and
saturation
Ultra-low-delay video processing
Audio and Video Interfaces
PAL or NTSC standard output and forcible standard
conversion
Aspect ratio of 4:3 or 16:9, forcible aspect ratio
conversion, and free scaling
4K@60 fps/50 fps/30 fps/25 fps, 1080p@60 fps/50 fps/30
fps/24 fps, 1080i@60 fps/50 fps, and
720p/576p/576i/480p/480i outputs
HD and SD outputs
One HDMI 2.0a TX with HDCP 2.2 output, supporting
maximum 4K x 2K@60 fps resolution
Analog video interfaces
− One CVBS interface
− One internal VDAC
Audio interface
− Audio-left and audio-right outputs
− One internal ADAC
− One I
2
S or PCM digital audio input or output
− HDMI audio output
Peripheral Interfaces
Three USB 2.0 host ports
One 10 Mbit/s or 100 Mbit/s adaptive Ethernet port
(embedded FE PHY)
One 4-bit SDIO 3.0 interface
Three UART interfaces
One IR receiver
One LED and keypad control interface
Three I
2
C interfaces
Multiple groups of GPIO interfaces
One embedded POR
Others
Various boot modes
Boot program downloading and execution over a serial
port or USB port
Integrated dedicated standby processor, supporting various
low-power modes and less than 30 mW standby power
consumption
Passive standby and low-power design
14 mm x 14 mm (0.55 in. x 0.55 in.) BGA package,
supporting the 2-layer PCB