Micron美光NandFlash2G数据手册onfi1.0协议-MT29F2Gx

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包函镁光/美光2GNandFlash芯片数据手册--MT29F2G08ABAEAH4, MT29F2G08ABAEAWP, MT29F2G08ABBEAH4，MT29F2G08ABBEAHC, MT29F2G16ABAEAWP，MT29F2G16ABBEAH4，MT29F2G16ABBEAHC 美光NAND Flash数据手册MT29F2Gx系列详细介绍了多款基于ONFI 1.0协议的2Gb NAND Flash存储芯片，具体包括MT29F2G08ABAEAH4、MT29F2G08ABAEAWP、MT29F2G08ABBEAH4、MT29F2G08ABBEAHC、MT29F2G16ABAEAWP、MT29F2G16ABBEAH4和MT29F2G16ABBEAHC等型号。这些芯片采用单级单元（SLC）技术，拥有2Gb的存储容量，分为x8和x16的数据输出配置，支持2112字节（2048+64字节）的页面大小和1056字（1024+32字）的页面大小配置，以及128K+4K字节的块大小。该系列NAND Flash芯片支持异步I/O性能，其读页时间为25微秒，写页时间为200微秒（典型值在1.8V和3.3V下），而块擦除时间为700微秒。其数据保留时间为10年，编程/擦除循环耐久度高达10万次。工作电压范围分为两个部分，VCC范围为2.7-3.6V，而VCCQ范围为1.7-1.95V。芯片在出厂时，第一个块（地址为00h的块）带有ECC（错误校正码），若编程/擦除次数少于1000次，则块0需要1位ECC。同时，芯片采用了ONFI 1.0标准兼容的设计，支持高级命令集。操作状态字节允许软件检测操作完成或失败。芯片的封装类型包括48-pin TSOP类型1（CPL2）和63-ball VFBGA两种。不同的工作温度范围适用于不同的应用场合，包括商业级（0°C至+70°C）、工业级（-40ºC至+85ºC）、汽车级工业（-40°C至+85°C）和汽车级（-40°C至+105°C）。设备初始化有标准的复位操作和备用的Nand_Init方法，这些在电源开启后由工厂联系获取。芯片支持内部数据移动操作，能够在读取数据的平面内移动数据。设备还提供了一些特定的模式，例如程序页缓存模式、读页缓存模式、一次性可编程（OTP）模式，双平面命令和交错的LUN操作，以及区块锁定功能（只限1.8V）和读取唯一ID。这些NAND Flash芯片广泛应用于嵌入式系统、SSD、eMMC等存储解决方案中，为各种应用提供了可靠的存储性能和丰富的功能特性。通过对芯片性能、命令集、功能特性及封装类型的深入了解，开发者和工程师能够根据实际需求选择合适的存储芯片，以实现高效稳定的数据存储解决方案。

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NAND Flash Memory

MT29F2G08ABAEAH4, MT29F2G08ABAEAWP, MT29F2G08ABBEAH4

MT29F2G08ABBEAHC, MT29F2G16ABAEAWP, MT29F2G16ABBEAH4

MT29F2G16ABBEAHC

Features

• Open NAND Flash Interface (ONFI) 1.0-compliant

• Single-level cell (SLC) technology

• Organization

– Page size x8: 2112 bytes (2048 + 64 bytes)

– Page size x16: 1056 words (1024 + 32 words)

– Block size: 64 pages (128K + 4K bytes)

– Plane size: 2 planes x 1024 blocks per plane

– Device size: 2Gb: 2048 blocks

• Asynchronous I/O performance

–

RC/

WC: 20ns (3.3V), 25ns (1.8V)

• Array performance

– Read page: 25µs

– Program page: 200µs (TYP: 1.8V, 3.3V)

– Erase block: 700µs (TYP)

• Command set: ONFI NAND Flash Protocol

• Advanced command set

– Program page cache mode

– Read page cache mode

– One-time programmable (OTP) mode

– Two-plane commands

– Interleaved die (LUN) operations

– Read unique ID

– Block lock (1.8V only)

– Internal data move

• Operation status byte provides software method for

detecting

– Operation completion

– Pass/fail condition

– Write-protect status

• Ready/Busy# (R/B#) signal provides a hardware

method of detecting operation completion

• WP# signal: Write protect entire device

• First block (block address 00h) is valid when ship-

ped from factory with ECC. For minimum required

ECC, see Error Management.

• Block 0 requires 1-bit ECC if PROGRAM/ERASE cy-

cles are less than 1000

• RESET (FFh) required as first command after pow-

er-on

• Alternate method of device initialization (Nand_In-

it) after power up (contact factory)

• Internal data move operations supported within the

plane from which data is read

• Quality and reliability

– Data retention: 10 years

– Endurance: 100,000 PROGRAM/ERASE cycles

• Operating voltage range

– V

: 2.7–3.6V

– V

: 1.7–1.95V

• Operating temperature

– Commercial: 0°C to +70°C

– Industrial (IT): –40ºC to +85ºC

– Automotive Industrial (AIT): –40°C to +85°C

– Automotive (AAT): –40°C to +105°C

• Package

– 48-pin TSOP type 1, CPL

– 63-ball VFBGA

Notes:

1. The ONFI 1.0 specification is available at

www.onfi.org.

2. CPL = Center parting line.

3. See Electrical Specifications – Program/Erase

Characteristics for

R_ECC and

PROG_ECC

specifications.

4. These commands supported only with ECC

disabled.

Micron Confidential and Proprietary

2Gb: x8, x16 NAND Flash Memory

Features

PDF: 09005aef83b83f42

m69a_2gb_ecc_nand.pdf - Rev. R 04/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Products and specifications discussed herein are subject to change by Micron without notice.

Contents

General Description ......................................................................................................................................... 8

Signal Descriptions ........................................................................................................................................... 8

Signal Assignments ........................................................................................................................................... 9

Package Dimensions ....................................................................................................................................... 12

Architecture ................................................................................................................................................... 15

Device and Array Organization ........................................................................................................................ 16

Asynchronous Interface Bus Operation ........................................................................................................... 18

Asynchronous Enable/Standby ................................................................................................................... 18

Asynchronous Commands .......................................................................................................................... 18

Asynchronous Addresses ............................................................................................................................ 20

Asynchronous Data Input ........................................................................................................................... 21

Asynchronous Data Output ......................................................................................................................... 22

Write Protect# ............................................................................................................................................ 23

Ready/Busy# .............................................................................................................................................. 23

Device Initialization ....................................................................................................................................... 28

Command Definitions .................................................................................................................................... 29

Reset Operations ............................................................................................................................................ 32

RESET (FFh) ............................................................................................................................................... 32

Identification Operations ................................................................................................................................ 33

READ ID (90h) ............................................................................................................................................ 33

READ ID Parameter Tables .............................................................................................................................. 34

READ PARAMETER PAGE (ECh) ...................................................................................................................... 36

Parameter Page Data Structure Tables ............................................................................................................. 37

READ UNIQUE ID (EDh) ................................................................................................................................ 41

Feature Operations ......................................................................................................................................... 42

SET FEATURES (EFh) .................................................................................................................................. 43

GET FEATURES (EEh) ................................................................................................................................. 44

Status Operations ........................................................................................................................................... 47

READ STATUS (70h) ................................................................................................................................... 48

READ STATUS ENHANCED (78h) ................................................................................................................ 48

Column Address Operations ........................................................................................................................... 50

RANDOM DATA READ (05h-E0h) ................................................................................................................ 50

RANDOM DATA READ TWO-PLANE (06h-E0h) ............................................................................................ 51

RANDOM DATA INPUT (85h) ...................................................................................................................... 52

PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 53

Read Operations ............................................................................................................................................. 55

READ MODE (00h) ..................................................................................................................................... 57

READ PAGE (00h-30h) ................................................................................................................................ 57

READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 58

READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 59

READ PAGE CACHE LAST (3Fh) .................................................................................................................. 61

READ PAGE TWO-PLANE 00h-00h-30h ....................................................................................................... 62

Program Operations ....................................................................................................................................... 64

PROGRAM PAGE (80h-10h) ......................................................................................................................... 65

PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 65

PROGRAM PAGE TWO-PLANE (80h-11h) .................................................................................................... 68

Erase Operations ............................................................................................................................................ 70

ERASE BLOCK (60h-D0h) ............................................................................................................................ 70

ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 71

Internal Data Move Operations ....................................................................................................................... 72

Micron Confidential and Proprietary

2Gb: x8, x16 NAND Flash Memory

Features

PDF: 09005aef83b83f42

m69a_2gb_ecc_nand.pdf - Rev. R 04/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 73

PROGRAM FOR INTERNAL DATA MOVE (85h–10h) ..................................................................................... 74

PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) ................................................................. 75

Block Lock Feature ......................................................................................................................................... 76

WP# and Block Lock ................................................................................................................................... 76

UNLOCK (23h-24h) .................................................................................................................................... 76

LOCK (2Ah) ................................................................................................................................................ 79

LOCK TIGHT (2Ch) ..................................................................................................................................... 80

BLOCK LOCK READ STATUS (7Ah) .............................................................................................................. 81

One-Time Programmable (OTP) Operations .................................................................................................... 83

Legacy OTP Commands .............................................................................................................................. 83

OTP DATA PROGRAM (80h-10h) ................................................................................................................. 84

RANDOM DATA INPUT (85h) ...................................................................................................................... 85

OTP DATA PROTECT (80h-10) ..................................................................................................................... 86

OTP DATA READ (00h-30h) ......................................................................................................................... 88

Two-Plane Operations .................................................................................................................................... 90

Two-Plane Addressing ................................................................................................................................ 90

Interleaved Die (Multi-LUN) Operations .......................................................................................................... 99

Error Management ........................................................................................................................................ 100

Internal ECC and Spare Area Mapping for ECC ............................................................................................... 102

Electrical Specifications ................................................................................................................................. 104

Electrical Specifications – DC Characteristics and Operating Conditions .......................................................... 106

Electrical Specifications – AC Characteristics and Operating Conditions .......................................................... 108

Electrical Specifications – Program/Erase Characteristics ................................................................................ 111

Asynchronous Interface Timing Diagrams ...................................................................................................... 112

Revision History ............................................................................................................................................ 124

Rev. R – 04/14 ............................................................................................................................................ 124

Rev. Q – 02/14 ............................................................................................................................................ 124

Rev. P – 08/13 ............................................................................................................................................ 124

Rev. O – 10/12 ............................................................................................................................................ 124

Rev. N – 02/12 ............................................................................................................................................ 124

Rev. M – 01/12 ........................................................................................................................................... 124

Rev. L – 11/11 ............................................................................................................................................ 124

Rev. K – 01/11 ............................................................................................................................................ 124

Rev. J – 12/10 ............................................................................................................................................. 124

Rev. I – 11/10 ............................................................................................................................................. 124

Rev. H – 09/10 ............................................................................................................................................ 124

Rev. G – 08/10 ............................................................................................................................................ 125

Rev. F – 06/10 ............................................................................................................................................ 125

Rev. E – 05/10 ............................................................................................................................................ 125

Rev. D – 03/10 ............................................................................................................................................ 125

Rev. C – 01/10 ............................................................................................................................................ 125

Rev. B – 09/09 ............................................................................................................................................ 125

Rev. A – 07/09 ............................................................................................................................................ 125

Micron Confidential and Proprietary

2Gb: x8, x16 NAND Flash Memory

Features

PDF: 09005aef83b83f42

m69a_2gb_ecc_nand.pdf - Rev. R 04/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

List of Tables

Table 1: Signal Definitions ............................................................................................................................... 8

Table 2: Array Addressing – MT29F2G08 (x8) .................................................................................................. 16

Table 3: Array Addressing – MT29F2G16 (x16) ................................................................................................. 17

Table 4: Asynchronous Interface Mode Selection ............................................................................................ 18

Table 5: Command Set .................................................................................................................................. 29

Table 6: Two-Plane Command Set .................................................................................................................. 31

Table 7: READ ID Parameters for Address 00h ................................................................................................. 34

Table 8: READ ID Parameters for Address 20h ................................................................................................. 35

Table 9: Parameter Page Data Structure .......................................................................................................... 37

Table 10: Feature Address Definitions ............................................................................................................. 42

Table 11: Feature Address 90h – Array Operation Mode ................................................................................... 43

Table 12: Feature Addresses 01h: Timing Mode ............................................................................................... 45

Table 13: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 46

Table 14: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 46

Table 15: Status Register Definition ................................................................................................................ 47

Table 16: Block Lock Address Cycle Assignments ............................................................................................ 78

Table 17: Block Lock Status Register Bit Definitions ........................................................................................ 81

Table 18: Error Management Details ............................................................................................................. 100

Table 19: Absolute Maximum Ratings ............................................................................................................ 104

Table 20: Recommended Operating Conditions ............................................................................................. 104

Table 21: Valid Blocks ................................................................................................................................... 104

Table 22: Capacitance ................................................................................................................................... 105

Table 23: Test Conditions .............................................................................................................................. 105

Table 24: DC Characteristics and Operating Conditions (3.3V) ....................................................................... 106

Table 25: DC Characteristics and Operating Conditions (1.8V) ....................................................................... 107

Table 26: AC Characteristics: Command, Data, and Address Input (3.3V) ........................................................ 108

Table 27: AC Characteristics: Command, Data, and Address Input (1.8V) ........................................................ 108

Table 28: AC Characteristics: Normal Operation (3.3V) .................................................................................. 109

Table 29: AC Characteristics: Normal Operation (1.8V) .................................................................................. 109

Table 30: Program/Erase Characteristics ....................................................................................................... 111

Micron Confidential and Proprietary

2Gb: x8, x16 NAND Flash Memory

Features

PDF: 09005aef83b83f42

m69a_2gb_ecc_nand.pdf - Rev. R 04/14 EN