Vincent Bligny

The Entire Semiconductor Industry — Explained in One Chart Chips don’t come from a single company. They come from a global symphony of players — each mastering a step in the semiconductor value chain. Here’s how it all breaks down: → Design (IP) Arm, Imagination The blueprint stage. These companies design instruction sets and microarchitectures used by almost every modern SoC. → EDA Tools Synopsys, Cadence, TestFlow The invisible engines of chip creation and testing. Their tools let engineers simulate, test, and tape-out billion-transistor chips. → Fabless Designers NVIDIA, Apple, Qualcomm, AMD They design chips but outsource manufacturing — betting everything on innovation and execution. → Foundries TSMC, UMC, GlobalFoundries The builders. These are the ultra-precise factories that turn blueprints into working silicon. → Integrated Device Manufacturers (IDMs) Intel, Samsung, Texas Instruments They do it all — design, manufacture, package, and sell. Think vertical integration at massive scale. → Raw Materials Shin-Etsu, Siltronic, SUMCO No wafers, no chips. These players supply the pure silicon and gases needed for fabrication. → Equipment Vendors ASML, Applied Materials, Lam Research These companies make the ultra-complex machines that build chips — like EUV scanners and etchers. → Testing & Packaging Amkor, Advantest, Teradyne Before chips ship, they’re packaged, tested, and binned. These firms ensure reliability at nanometer scale. Key takeaway: The semiconductor world isn’t one company — it’s a global supply chain of extreme complexity. Disrupt one link, and the whole world feels it — from smartphones to AI servers. P.S. Want more breakdowns like this? Check out our blog The Semiconductor World — link in comments. #Semiconductors #Chips #TSMC #NVIDIA #EDA #ASML #ChipDesign #Foundry #SupplyChain #TestFlow #TheSemiconductorWorld #AI

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UBM (Under Bump Metallization) Purpose: UBM is a critical layer in advanced semiconductor packaging, enabling reliable electrical and mechanical connections between the chip and solder bumps or copper pillars. Functions: Provides electrical interconnection, wetting for solder, diffusion barrier, and mechanical support. Prevents failures like delamination, solder voids, and electromigration. Applications: Used in Flip-Chip, Wafer-Level Packaging (WLP), Fan-Out WLP, 2.5D/3D IC stacking, and high-end 3D packaging (e.g., HBM, CoWoS). Materials: Multi-layer stacks: adhesion (Ti, TiW, Ta), seed/conductor (Cu), barrier (TiN, Ta, Ni), wetting (Au, Ag), and solder (Sn, SnAgCu). Etching: Selective etchants are used for each metal layer (e.g., HF+H₂O₂ for Ti, H₃PO₄+H₂O₂ for Cu, KI/I₂ for Au). Process control is crucial to avoid over-etching and ensure pad accuracy. Trends: Moving toward finer pitches (<50 μm), eco-friendly chemistries, cost reduction (less Au), and dry/plasma etching for better precision. Conclusion: UBM is foundational for next-gen semiconductor reliability, yield, and performance, especially as packaging becomes more complex and dense.

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Clock jitter refers to the variation of a clock signal’s edge from its ideal position in time. It is critical in high-speed digital, mixed-signal, and communication systems because it affects timing margins, setup/hold requirements, and data integrity. ⸻ ✅ Types of Clock Jitter Here are the major types: 1. Period Jitter • Definition: Variation in the clock period from one cycle to the next. • Impact: • Causes frequency instability. • Can lead to setup/hold violations in synchronous systems. • Example: One clock cycle is 10.1 ns, the next is 9.9 ns instead of the ideal 10 ns. ⸻ 2. Cycle-to-Cycle Jitter • Definition: Difference in duration between two adjacent cycles. • Impact: • Critical in high-speed I/O and SerDes designs. • Affects PLL/DLL performance and data serialization/deserialization. ⸻ 3. Long-Term Jitter (or Accumulated Jitter) • Definition: Cumulative deviation of clock edges over a long time. • Impact: • Important in systems with multiple clock domains and data recovery. • Causes phase drift and synchronization issues. ⸻ 4. Random Jitter (RJ) • Definition: Caused by thermal noise and other stochastic processes. • Characteristics: • Unbounded, follows a Gaussian distribution. • Impact: • Dominates at very high frequencies. • Reduces timing margin for setup/hold. ⸻ 5. Deterministic Jitter (DJ) • Definition: Jitter that has a bounded, predictable cause. • Sources: • Crosstalk, power supply noise, EMI, clock interference. • Impact: • Can be analyzed and reduced by design improvements. ⸻ 6. Duty Cycle Distortion (DCD) • Definition: Variation in high and low times of the clock. • Impact: • Alters duty cycle, which can affect latch/flip-flop operation. • Critical in DDR memory and high-speed buses. ⸻ 7. Phase Jitter • Definition: Short-term variations in the phase of the clock signal. • Impact: • Affects PLL lock stability and clock data recovery (CDR). ⸻ ✅ Impact on Design 1. Timing Violations • Jitter reduces the effective setup and hold margins. • In STA (Static Timing Analysis), jitter is modeled as clock uncertainty. 2. Signal Integrity • High jitter increases bit error rate (BER) in high-speed links (e.g., PCIe, DDR, SerDes). 3. PLL/DLL Design • Jitter tolerance is key in clock generation and recovery circuits. 4. Synchronous System Stability • More jitter → skew variations, synchronization failures. ⸻ How It’s Handled in Design • Clock uncertainty in STA = Jitter + Skew. • Jitter budget allocation among PLL, clock tree, and data paths. • Low-noise power supply design (reduce supply-induced jitter). • Use of spread-spectrum clocking to minimize EMI-based jitter. • Filtering (PLL bandwidth) to suppress high-frequency jitter.

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Is There Still A Future For Hard Disk Drives? The cost of HDDs and SSDs will continue to fall, while capacity will continue to increase in both. The capacity for solid state drives (#SSDs) keeps going up while the price per terabyte keeps falling, sometimes raising questions about the future for hard disk drives (#HDDs). Will the cost of #SSDs per TB eventually become so low that they will totally displace HDDs? Barry Pangrle decided to ask a couple of experts in the field, Jim Handy from Objective Analysis and Thomas Coughlin of Coughlin Associates. He was looking for a comparison projection for HDDs and SSDs that would go about five years out into the future. Jim had performed such an exercise back in 2017, WDC: No SSD/HDD Crossover,but I needed something more recent. Jim had his SSD forecast data, shown in red in Figure 1 and Tom provided the HDD data shown in blue. The slope is steeper for the #SSD data, but it does not look like we’ll see a crossover in the next 5 years. The green $4.75/TB point was placed there by Barry to show readers where that falls on the plot and to use again later in another chart.... A very big thank you to Barry Pangrle , Jim Handy , Thomas Coughlin and Semiconductor Engineering for this very interesting full comparison/article with more background and insights via the link below 💡🙏👇 https://lnkd.in/eKTxfR7P #semiconductorindustry #semiconductor #technology #tech #chip #chips #it #datacenter #technology #memory #storage #computer #ssd #hdd

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RF Basics: Up-Conversion Mixer An up-conversion mixer is an essential component in RF and microwave systems, particularly in transmitters, that serves to increase the frequency of an input signal. It takes an intermediate frequency (IF) signal as input and combines it with a higher frequency local oscillator (LO) signal to produce an output radio frequency (RF) signal, according to Microwaves & RF. This output frequency is typically the sum of the IF and LO frequencies. How it works: The core principle behind an up-conversion mixer is the non-linear interaction of two signals. When the IF and LO signals are fed into a mixer, they pass through a non-linear element (like a diode or transistor) that effectively multiplies them together. This multiplication generates new frequencies, including the sum (fLO + fIF) and difference (fLO - fIF) of the input frequencies. In up-conversion, the desired output is the sum frequency, which is typically filtered out and amplified for transmission. Key characteristics and parameters: Frequency Range: The operational frequency range for the IF, LO, and RF ports. Conversion Gain: Measures the mixer's ability to amplify the signal during up-conversion. Linearity (1 dB Compression Point): Indicates the mixer's ability to handle high input power without distortion. Isolation: Refers to the separation of signals between different ports (e.g., LO to RF isolation) to minimize leakage and interference. Noise Figure: Represents the noise introduced by the mixer, which can degrade the signal-to-noise ratio. Types of up-conversion mixers: Active Mixers: Utilize active components like transistors to provide conversion gain and reduce LO drive requirements, according to Analog Devices. However, they often have a higher noise figure and lower linearity compared to passive mixers. Passive Mixers: Rely on passive components like diodes and don't require external power. They offer high linearity and wide bandwidth but may introduce signal loss. Applications: Up-conversion mixers are crucial components in various applications. Wireless communication systems: Cellular networks, Wi-Fi, and Bluetooth all rely on up-conversion to transmit signals at different frequencies. Radar Systems: Up-conversion mixers are used in radar transmitters to convert low-frequency signals to the high-frequency radar signals for transmission. Satellite communication systems: Essential for uplink communication to shift signals to higher frequencies for transmission to satellites. Test and measurement equipment: Found in signal generators and spectrum analyzers for precise frequency generation and analysis. Up-conversion mixers are vital for efficient and reliable signal transmission in a wide range of modern electronic systems. Their ability to precisely translate signals to higher frequencies is fundamental to many wireless technologies. 🙏🙏🙏🙏🙏

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𝐃𝐢𝐫𝐞𝐜𝐭 𝐀𝐧𝐭𝐞𝐧𝐧𝐚 𝐑𝐮𝐥𝐞𝐬 𝐢𝐧 𝐀𝐧𝐚𝐥𝐨𝐠 𝐋𝐚𝐲𝐨𝐮𝐭 – 𝐖𝐡𝐲 𝐓𝐡𝐞𝐲 𝐌𝐚𝐭𝐭𝐞𝐫 In analog IC layout, precision isn’t just about device matching — it’s also about protecting delicate transistor gates during fabrication. One of the most overlooked yet critical factors is Direct Antenna Rules. What Are Direct Antenna Rules? During IC fabrication (especially during plasma etching), long metal interconnects connected to a MOS gate can act like an antenna, collecting and storing charge from the plasma. If the gate is not yet connected to the diffusion or source/drain (because those layers are patterned later), the accumulated charge has nowhere to go — and it can punch through the ultra-thin gate oxide. This is called antenna effect (or plasma-induced gate oxide damage). Why This Is a Bigger Issue in Analog Layout: Unlike digital cells (which are highly standardized), analog layouts often: Use longer routing paths for matching and symmetry Employ custom routing over multiple layers Handle large transistors with thin oxides (low-voltage devices) that are more vulnerable Thus, antenna violations are more likely if routing is not carefully planned. Direct Antenna Rule Definition: The Direct Antenna Ratio (DAR) is usually defined as: DAR=Area of metal connected to the gate before diffusion/Area of gate oxide Foundries specify a maximum DAR for each metal layer (e.g., Metal1, Metal2). If exceeded → antenna violation. Techniques to Avoid Direct Antenna Violations 1.Metal Jumping (Layer Hopping) – Route the gate to a higher metal layer early, then drop back down closer to diffusion. 2.Antenna Diodes – Place a diode from the gate net to diffusion for charge discharge. 3.Routing to Diffusion First – Connect gate to source/drain early in mask sequence. 4.Dummy Gates – Add extra gate area to reduce DAR ratio. 5.Metal Segmentation – Break the metal path into smaller pieces connected later. Analog-Specific Best Practices: Symmetry Awareness – Ensure antenna fixes don’t disrupt matching in differential pairs. Shielding Caution – Shield lines with grounded metal but recheck DAR after shielding. LVS + Antenna Checks – Always run foundry antenna DRC rules before tape-out. 📩 Want to Master Analog Layout & Tape-Out Practices? Apply here → https://lnkd.in/dZi8JDQA 📱 WhatsApp → https://lnkd.in/g9wNMycs 📡 Telegram → https://t.me/AnalogIC_RFIC #AnalogDesign #VLSI #AnalogLayout #SemiconductorDesign #AnalogIC #AMSVerification #AnalogEngineering #CustomLayout #EDA #Tapeout #ChipDesign #LayoutDesign #MixedSignalDesign #AnalogTips #ICLayout #CircuitDesign #AnalogICDesign #LayoutBestPractices #SemiconductorIndustry

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Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. TT-Ascalon is Tenstorrent’s high-performance RISC-V CPU, built on open standards to provide maximum flexibility and architectural control. It is based on the open RISC-V ISA and is RVA23 compliant. A central focus of the Ashling–Tenstorrent collaboration is comprehensive trace support, built on the RISC-V standard N-Trace architecture. RiscFree integrates with Tenstorrent’s Ascalon CPUs to capture detailed trace data across multi-core systems, enabling real-time visibility into instruction execution, memory transactions, and key system events. In addition to N-Trace, Tenstorrent’s Debug Signal Trace (DST) infrastructure has been fully implemented in its Ascalon CPUs, providing access to critical micro-architectural signals alongside standard trace data during post-silicon validation. DST enhances debugging, performance analysis, and coverage, and is fully supported by Ashling’s RiscFree tools—enabling deep trace visibility with minimal integration overhead. Learn more here: https://lnkd.in/gthF_9uj #RISCVEverwhere #DEBUG #Tenstorrent

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