EttusResearch / uhd
The USRP™ Hardware Driver Repository
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The USRP™ Hardware Driver Repository
PicoRV32 - A Size-Optimized RISC-V CPU
HDL libraries and projects
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
Verilog Ethernet components for FPGA implementation
An Open-source FPGA IP Generator
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!