Circuit diagram of linear-feedback shift register.

Can We Replace A Program Counter With A Linear-Feedback Shift Register? Yes We Can!

May 31, 2025 by John Elliot V 32 Comments

Today we heard from [Richard James Howe] about his new CPU. This new 16-bit CPU is implemented in VHDL for an FPGA.

The really cool thing about this CPU is that it eschews the typical program counter (PC) and replaces it with a linear-feedback shift register (LFSR). Apparently an LFSR can be implemented in hardware with fewer transistors than are required by an adder.

Usually the program counter in your CPU increments by one, each time indicating the location of the next instruction to fetch and execute. When you replace your program counter with an LFSR it still does the same thing, indicating the next instruction to fetch and execute, but now those instructions are scattered pseudo-randomly throughout your address space!

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IcePI Zero: A Pi Zero For FPGA

May 29, 2025 by Tyler August 32 Comments

The Rasberry Pi Zero is a delightful form factor, with its GIPO and USB and HDMI, but it’s stuck using the same old ARM processor all the time. What if you wanted to change it up with some OpenSPARC, RISC V, OpenPOWER, or even your own oddball homebrew ISA and processor? Well, fret not, for [Chengyin Yao]’s IcePi Zero has got you covered with its ECP5 25F FPGA.

As the saying goes, you don’t tell an FPGA what to do, you tell it what to be. And with the ECP5 25F’s 24k LUTs, you can tell it to be quite a few different things. This means more work for the maker than plugging in a fixed processor, sure, but IcePi tries to make that as painless as possible with quality-of-life features like HDMI out (something missing from many FPGA dev boards), an onboard USB-to-JTAG converter (so you can just plug it in, no programmer needed), and even USB-C instead of the Pi’s old microUSB. There’s the expected SD card on one end, and 256 MiB of 166 MHz SDRAM on the other to make up for the FPGA’s paltry 112 KiB of onboard RAM.

Plus it’s a drop-in replacement for the Pi Zero, so if you’ve already got a project that’s got one of those running an emulator, you can fab one of these babies, spool up some Verilog, and enjoy running on bare metal. It seems like this device is just made for retro gaming handhelds, but we’d love to hear in the comments if you have other ideas what to do with this board– remember that an FPGA can be (almost) anything, even a GPU!

Currently, [Chengin Yao] is not selling the board, though they may reconsider due to demand in their Reddit thread. If you want one, you’ll have to call your favourite fabricator or etch your own PCB.

We’ve seen FPGAs before; most recently to create an absurdly fast 8080 processor. We’ve also seen DIY dev boards, like this one for the AMD Zyntac FPGA. Doing something fun with FPGAs? Drop us a tip! We’re happy [Chengin Yao] did, because this is amazing work, especially considering they are only 16 years old. We cannot wait to find out what they get up to next.

Two hands soldering components on a purpble PCB

Vintage Intel 8080 Runs On A Modern FPGA

May 26, 2025 by Heidi Ulrich 5 Comments

If you’re into retro CPUs and don’t shy away from wiring old-school voltages, [Mark]’s latest Intel 8080 build will surely spark your enthusiasm. [Mark] has built a full system board for the venerable 8080A-1, pushing it to run at a slick 3.125 MHz. Remarkable is that he’s done so using a modern Microchip FPGA, without vendor lock-in or proprietary flashing tools. Every step is open source.

Getting this vintage setup to work required more than logical tinkering. Mark’s board supplies the ±5 V and +12 V rails the 8080 demands, plus clock and memory interfacing via the M2GL005-TQG144I FPGA. The design is lean: two-layer PCB, basic level-shifters, and a CM32 micro as USB-to-UART fallback. Not everything went smoothly: incorrect footprints, misrouted gate drivers, thermal runaway in the clock section; but he managed to tackle it.

What sets this project apart is the resurrection of a nearly 50-year-old CPU. It’s also, how thoroughly thought-out the modern bridge is—from bitstream loading via OpenOCD to clever debugging of crystal oscillator drift using a scope. [Mark]’s love of the architecture and attention to low-level detail makes this more than a show-off build.
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Various hardware components laid out on a workbench.

Working On Open-Source High-Speed Ethernet Switch

May 20, 2025 by John Elliot V 17 Comments

Our hacker [Andrew Zonenberg] reports in on his open-source high-speed Ethernet switch. He hasn’t finished yet, but progress has been made.

If you were wondering what might be involved in a high-speed Ethernet switch implementation look no further. He’s been working on this project, on and off, since 2012. His design now includes a dizzying array of parts. [Andrew] managed to snag some XCKU5P FPGAs for cheap, paying two cents in the dollar, and having access to this fairly high-powered hardware affected the project’s direction.

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MiSTer For Mortals: Meet The Multisystem 2

May 19, 2025 by Heidi Ulrich 21 Comments

If you’ve ever squinted at a DE10-Nano wondering where the fun part begins, you’re not alone. This review of the Mr. MultiSystem 2 by [Lee] lifts the veil on a surprisingly noob-friendly FPGA console that finally gets the MiSTer experience out of the tinker cave and into the living room. Developed by Heber, the same UK wizards behind the original MultiSystem, this follow-up console dares to blend flexibility with simplicity. No stack required.

It comes in two varieties, to be precise: with, or without analog ports. The analog edition features a 10-layer PCB with both HDMI and native RGB out, Meanwell PSU support, internal USB headers, and even space for an OLED or NFC reader. The latter can be used to “load” physical cards cartridge-style, which is just ridiculously charming. Even the 3D-printed enclosure is open-source and customisable – drill it, print it, or just colour it neon green. And for once, you don’t need to be a soldering wizard to use the thing. The FPGA is integrated in the mainboard. No RAM modules, no USB hub spaghetti. Just add some ROMs (legally, of course), and you’re off.

Despite its plug-and-play aspirations, there are some quirks – for example, the usual display inconsistencies and that eternal jungle of controller mappings. But hey, if that’s the price for versatility, it’s one you’d gladly pay. And if you ever get stuck, the MiSTer crowd will eat your question and spit out 12 solutions. It remains 100% compatible with the MiSTer software, but allows some additional future features, should developers wish to support them.

Want to learn more? This could be your entrance to the MiSTer scene without having to first earn a master’s in embedded systems. Will this become an alternative to the Taki Udon announced Playstation inspired all-in-one FPGA console? Check the video here and let us know in the comments. Continue reading “MiSTer For Mortals: Meet The Multisystem 2” →

Building A Custom Zynq-7000 SoC Development Board From The Ground Up

April 20, 2025 by John Elliot V 8 Comments

In this series of 23 YouTube videos [Rich] puts the AMD Zynq-7000 SoC through its paces by building a development board from the ground up to host it along with its peripherals. The Zynq is part FPGA and part CPU, and while it has been around for a while, we don’t see nearly as many projects about it as we’d like.

[Rich] covers everything from the power system to HDMI, USB, DDR RAM, and everything in between. By the end, he’s able to boot PetaLinux.

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A slide from a talk about Spade language with a diagram about how it fits in with Verilog, VHDL, and HLS.

The Spade Hardware Description Language

April 13, 2025 by John Elliot V 15 Comments

Spade is an open-source hardware description language (HDL) developed at Linköping University, Sweden.

Other HDLs you might have heard of include Verilog and VHDL. Hardware engineers use HDLs to define hardware which can be rendered in silicon. Hardware defined in HDLs might look like software, but actually it’s not software, it’s hardware description. This hardware can be realized myriad ways including in an FPGA or with an ASIC.

You have probably heard that your CPU processes instructions in a pipeline. Spade has first-class support for such pipelines. This means that design activities such as re-timing and re-pipelining are much easier than in other HDLs where the designer has to implement these by hand. (Note: backward justification is NP-hard, we’re not sure how Spade supports this, if it does at all. If you know please enlighten us in the comments!)

Spade implements a type system for strong and static typing inspired by the Rust programming language and can do type inference. It supports pattern matching such as you might see in a typical functional programming language. It boasts having user-friendly and helpful error messages and tooling.

Spade is a work in progress so please expect missing features and breaking changes. The documentation is in The Spade Book. If you’re interested you can follow development on GitLab or Discord.

So now that you know about the Spade language, are you planning to take it for a spin? You will find plenty of Verilog/VHDL designs at Hackaday which you could re-implement using Spade, such as an easy one like Breathing LED Done With Raw Logic Synthesized From A Verilog Design (see benchmarks) or a much more challenging one like Game Boy Recreated In Verilog. If you give Spade a go we’d love to see what you come up with!

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