verilog-0.0.5: Verilog parser and DSL.

Safe HaskellSafe-Inferred

Language.Verilog.AST

Documentation

type Identifier = StringSource

data Module Source

Constructors

Module Identifier [Identifier] [ModuleItem] 

Instances

data ModuleItem Source

Constructors

Parameter (Maybe Range) Identifier Expr 
Localparam (Maybe Range) Identifier Expr 
Input (Maybe Range) [Identifier] 
Output (Maybe Range) [Identifier] 
Inout (Maybe Range) [Identifier] 
Wire (Maybe Range) [(Identifier, Maybe Expr)] 
Reg (Maybe Range) [(Identifier, Maybe Range)] 
Integer [Identifier] 
Initial Stmt 
Always Sense Stmt 
Assign LHS Expr 
Instance Identifier [PortBinding] Identifier [PortBinding] 

Instances

data Stmt Source

Constructors

Block (Maybe Identifier) [Stmt] 
StmtReg (Maybe Range) [(Identifier, Maybe Range)] 
StmtInteger [Identifier] 
Case Expr [Case] Stmt 
BlockingAssignment LHS Expr 
NonBlockingAssignment LHS Expr 
For (Identifier, Expr) Expr (Identifier, Expr) Stmt 
If Expr Stmt Stmt 
StmtCall Call 
Delay Expr Stmt 
Null 

Instances

data LHS Source

Constructors

LHS Identifier 
LHSBit Identifier Expr 
LHSRange Identifier Range 

Instances

data Expr Source

Constructors

String String 
Number BitVec 
ConstBool Bool 
ExprLHS LHS 
ExprCall Call 
UniOp UniOp Expr 
BinOp BinOp Expr Expr 
Mux Expr Expr Expr 
Repeat Expr [Expr] 
Concat [Expr] 

Instances

data UniOp Source

Constructors

Not 
BWNot 
UAdd 
USub 

Instances

data BinOp Source

Constructors

And 
Or 
BWAnd 
BWXor 
BWOr 
Mul 
Div 
Mod 
Add 
Sub 
ShiftL 
ShiftR 
Eq 
Ne 
Lt 
Le 
Gt 
Ge 

Instances

data Sense Source

Constructors

Sense LHS 
SenseOr Sense Sense 
SensePosedge LHS 
SenseNegedge LHS 

Instances

data Call Source

Constructors

Call Identifier [Expr] 

Instances

type PortBinding = (Identifier, Maybe Expr)Source

type Case = ([Expr], Stmt)Source

type Range = (Expr, Expr)Source