Tanmoy Das

#TutorialSeries #130 🚀 𝐒𝐚𝐦𝐬𝐮𝐧𝐠 𝐇𝐢𝐫𝐢𝐧𝐠 𝐩𝐫𝐨𝐜𝐞𝐬𝐬 𝐟𝐨𝐫 𝐄𝐂𝐄 𝐒𝐭𝐮𝐝𝐞𝐧𝐭𝐬🥇 For many ECE engineers, Samsung Semiconductor is a dream destination. With India becoming a hub for chip design and verification, the opportunities in VLSI are bigger than ever. But the hiring process is intense—and very different from typical software interviews. 𝐇𝐞𝐫𝐞’𝐬 𝐚 𝐛𝐫𝐞𝐚𝐤𝐝𝐨𝐰𝐧 𝐨𝐟 𝐭𝐡𝐞 𝐒𝐚𝐦𝐬𝐮𝐧𝐠 𝐕𝐋𝐒𝐈 𝐡𝐢𝐫𝐢𝐧𝐠 𝐣𝐨𝐮𝐫𝐧𝐞𝐲 𝐟𝐨𝐫 𝐄𝐂𝐄 𝐬𝐭𝐮𝐝𝐞𝐧𝐭𝐬 👇 🔹 𝐒𝐭𝐚𝐠𝐞 1: 𝐄𝐥𝐢𝐠𝐢𝐛𝐢𝐥𝐢𝐭𝐲 & 𝐒𝐡𝐨𝐫𝐭𝐥𝐢𝐬𝐭𝐢𝐧𝐠 ▶️CGPA Cutoff: ~7.5 or higher. ▶️Branches: ECE, EEE, Instrumentation. 🔗https://lnkd.in/gfRYVJCr 👉 Tip: Highlight VLSI coursework, labs and internship/research projects on your resume. 🔹 𝐒𝐭𝐚𝐠𝐞 2: 𝐖𝐫𝐢𝐭𝐭𝐞𝐧 / 𝐎𝐧𝐥𝐢𝐧𝐞 𝐓𝐞𝐬𝐭 ▶️The biggest screening step. Usually a mix of core + aptitude. ▶️Electronics & VLSI topics: ✅Digital design (counters, FSMs, timing diagrams) ✅CMOS basics (Vt, leakage, scaling effects) ✅Device physics & semiconductor fundamentals ✅Verilog/VHDL coding & debugging STA basics, setup/hold violations ✅Aptitude: Quantitative + logical reasoning. ✅Coding (sometimes): Basic C or scripting (Python/Perl/TCL) for automation roles. 👉 Tip: Prepare from M. Morris Mano, Rabaey, Sedra/Smith and practice HDL problems. 🔹 𝐒𝐭𝐚𝐠𝐞 3: 𝐓𝐞𝐜𝐡𝐧𝐢𝐜𝐚𝐥 𝐈𝐧𝐭𝐞𝐫𝐯𝐢𝐞𝐰𝐬 (2–3 𝐫𝐨𝐮𝐧𝐝𝐬) ▶️Deep dive into your VLSI knowledge. ▶️Common areas tested: ✅Digital Electronics: Flip-flops, multiplexers, FSMs, hazards, timing analysis. ✅CMOS & Devices: Inverter characteristics, power-delay tradeoff, scaling. ✅HDL (Verilog/VHDL/SystemVerilog): ✅Write RTL code, explain testbenches, debug logic. ✅EDA Tools: Synopsys, Cadence basics; STA, synthesis, simulation. ✅Verification: Assertions, coverage, randomization, UVM basics. ✅Project Discussion: “How did you design/verify this block? What optimizations did you make?” 👉 Tip: Be ready to write code on a whiteboard / online pad (e.g., Verilog module for a priority encoder with testbench). 🔹 𝐒𝐭𝐚𝐠𝐞 4: 𝐇𝐑 / 𝐁𝐞𝐡𝐚𝐯𝐢𝐨𝐫𝐚𝐥 𝐑𝐨𝐮𝐧𝐝 ▶️Checks culture-fit, passion, and long-term vision. ▶️Why VLSI? Why Samsung? ▶️How do you see yourself growing in the semiconductor industry? 👉 Tip: Show awareness of Samsung Foundry, 5nm/3nm nodes, AI/automotive chips—connect your interests to their roadmap. 🌟 𝐅𝐢𝐧𝐚𝐥 𝐓𝐚𝐤𝐞𝐚𝐰𝐚𝐲𝐬 ✅ Master digital + CMOS fundamentals—these are always tested. ✅ Practice HDL coding regularly. ✅ Understand EDA flow. ✅ Talk confidently about projects—even an FPGA mini-project can shine if explained well. 🔁 Follow SAMAGATA SEMICONDUCTORS COMMUNITY in linkdin, join Whatsapp group( https://lnkd.in/g3RCDTvG ) and follow on Instagram(https://lnkd.in/gjJbDcRj) for career tips, VLSI insights and tech updates. #Semiconductors #VLSI #VirtualLabs #IIT #NIT #ECE #BTech #MTech #cfbr #Innovation #AnalogDesign #DigitalDesign #FreeTools #SamagataSemiconductors

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𝐈𝐧𝐝𝐢𝐚’𝐬 𝐒𝐞𝐦𝐢𝐜𝐨𝐧𝐝𝐮𝐜𝐭𝐨𝐫 𝐇𝐢𝐫𝐢𝐧𝐠 𝐒𝐮𝐫𝐠𝐞 𝐢𝐬 𝐑𝐞𝐝𝐞𝐟𝐢𝐧𝐢𝐧𝐠 𝐂𝐚𝐫𝐞𝐞𝐫𝐬! The semiconductor industry in India is experiencing an unprecedented hiring boom — gradually chipping away at IT placements and opening exciting opportunities for engineers across domains. 🔹 End-to-end hiring: RTL/SoC design, verification, embedded systems, manufacturing (process, packaging, yield). 🔹 Freshers’ salaries: ₹6–12 LPA (vs. ₹3–4 LPA in IT). 🔹 Aggressive campus recruitment from tier-2 & tier-3 colleges, not just IITs. 🔹 Internships: ₹40k–50k/month stipends to build hands-on chip design skills. 🔹 Hiring scale: ~12,000 freshers annually (up from 8,000 last year). 🔹 Career growth: Roles extend up to ₹20–120 LPA for architects & leaders. Fuelled by global supply chain shifts, EVs, telecom, defence, and government initiatives (DLI, PLI, ECMS), this hiring surge is reshaping student aspirations, especially in ECE and core engineering branches. With India projected to hit $103B semiconductor market by 2030, this is the right time for students and professionals to align their skills with VLSI, Embedded Systems, AI/ML hardware, and semiconductor manufacturing. The future is semiconductor — and India is powering ahead as a global hub! https://lnkd.in/gKtU5Gn2 #Semiconductor #VLSI #ChipDesign #EmbeddedSystems #Electronics #SoC #SemiconductorIndia #SemiconductorJobs #SemiconductorTalent #HiringTrends #Careers #ECE #Engineering #SemiconductorEcosystem #MakeInIndia #Innovation #ElectronicsManufacturing #FutureOfWork #AI #ML #Hardware #Manufacturing #IndiaSemiconductorMission

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7 key branches of semiconductors with leading companies & Applications 1. VLSI (Very Large Scale Integration): Leading Companies: Intel, Samsung, TSMC Applications: Microprocessors, Memory chips , ASICs 2. Power Semiconductors: Leading Companies: Infineon, STMicroelectronics Texas Instruments Applications: Electric vehicles (inverters, converters), Renewable energy 3. Analog Semiconductors: Leading Companies: Analog Devices, Texas Instruments, Maxim Integrated Applications: Audio & Video processing, Communication systems and RF circuits 4. Digital Semiconductors: Leading Companies: Intel, Qualcomm, Broadcom Applications:Microprocessors and microcontrollers, Memory chips (Flash memory, SSDs) 5. MEMS (Micro-Electro-Mechanical Systems): Leading Companies:Bosch Sensortec, STM, Analog Devices Applications:Accelerometers and gyroscopes in smartphones, Pressure sensors for automotive applications, Inkjet printer heads and microphones 6. Optoelectronics: Leading Companies:Cree, Nichia, Osram Applications:LEDs for displays, Optical communication, Photodetectors 7. Compound Semiconductors: Leading Companies:Cree, Qorvo, GaN Systems Applications:High-frequency RF (Radio Frequency) devices, Power amplifiers for wireless communication For all Semiconductors and AI related content, follow TechoVedas Add more branches in the comments. If you are looking to invest in semiconductors and looking for consulting, drop us a DM. #VLSI #AI #semiconductorindustry

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👉𝐘𝐨𝐮 𝐌𝐔𝐒𝐓 𝐤𝐧𝐨𝐰 𝐭𝐡𝐞𝐬𝐞 100 𝐓𝐂𝐋 𝐂𝐨𝐦𝐦𝐚𝐧𝐝𝐬 𝐛𝐞𝐟𝐨𝐫𝐞 𝐚𝐭𝐭𝐞𝐧𝐝𝐢𝐧𝐠 𝐏𝐡𝐲𝐬𝐢𝐜𝐚𝐥 𝐃𝐞𝐬𝐢𝐠𝐧 𝐈𝐧𝐭𝐞𝐫𝐯𝐢𝐞𝐰𝐬 Struggling to recall the right command during placement, routing, or STA rounds? This PDF brings you 100 essential TCL commands, each mapped to a key interview question – covering: 🔹 Floorplanning 🔹 Placement 🔹 Clock Tree Synthesis 🔹 Routing 🔹 Timing Analysis 🔹 Power & DRC 🔹 Optimization & Signoff Whether you're a physical design fresher or an experienced engineer prepping for your next move – this guide is your TCL survival kit. 👉 Join us and shape your future in VLSI! 👉 Our website : https://provlogic.com/ #VLSI #PhysicalDesign #TCL #ICDesign #STA #PDInterview #SemiconductorCareers #Cadence #Synopsys #PracticalVLSI #ChipDesign #PlacementToSignoff

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Memory paging in OS: Memory paging is a memory management scheme that eliminates the need for contiguous allocation of physical memory, thereby making more efficient use of available memory and simplifying memory allocation. 👉 Basic Idea 1️⃣ Paging: Divides the virtual memory into fixed-size blocks called pages and the physical memory into blocks of the same size called frames. 2️⃣ Virtual Memory: An abstraction that provides each process with the illusion of a large, contiguous address space. 3️⃣ Physical Memory: The actual RAM available in the system. 👉Key Components 1️⃣ Pages: Fixed-size blocks of virtual memory. Common sizes are 4 KB, 2 MB, or 1 GB. 2️⃣ Frames: Fixed-size blocks of physical memory that correspond in size to pages. 3️⃣ Page Table: A data structure used by the operating system to keep track of the mapping between virtual pages and physical frames. 👉 How Paging Works 1️⃣ Address Translation: When a program accesses a memory address, the virtual address is translated into a physical address using the page table. The virtual address consists of: Page Number: Indexes into the page table. Offset: Specifies the exact location within the page. 2️⃣ Page Table Lookup: The page table entry (PTE) for the page number provides the frame number. The frame number is combined with the offset to produce the physical address. 3️⃣ Page Faults: A page fault occurs if the required page is not in physical memory (not mapped to any frame). The operating system must bring the page from disk (swap space) into a free frame in physical memory and update the page table. 💪 Benefits of Paging 1️⃣ Eliminates Contiguous Allocation Requirement: Physical memory can be used more efficiently since any free frame can be used for any page. 2️⃣ Isolation and Protection: Each process operates in its own virtual address space, preventing one process from accessing the memory of another process. 3️⃣ Simplifies Memory Management: The operating system can manage memory in fixed-size blocks, simplifying allocation and deallocation. ✅ Summary Memory paging is a powerful technique that provides the benefits of virtual memory without the drawbacks of contiguous physical memory allocation. It allows systems to efficiently manage memory, ensure process isolation, and simplify memory allocation and deallocation through the use of fixed-size pages and frames. #paging #os #kernel #linux #embedded #learning #systemdesign

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🚀 Why Choosing VLSI as a Career in India (2025) Is a Brilliant Move With India rapidly emerging as a semiconductor powerhouse, VLSI (Very-Large-Scale Integration) is no longer just a niche—it’s the future. Here’s why this is one of the smartest career bets right now: 🔑 1. Massive Government Push ✅ ₹76,000 Cr India Semiconductor Mission (ISM) is fueling chip design & manufacturing ✅ “Make in India” & “Digital India” boosting demand for semiconductor talent ✅ New fabs (Micron, Tata in Gujarat) creating thousands of jobs 📈 2. Explosive Demand for Chips ✅ India is a top consumer of electronics: smartphones, EVs, IoT, 5G ✅ AI chips, edge devices, and automotive electronics are expanding VLSI’s scope 🧠 3. Surging Job Opportunities ✅ Fabless companies, design service firms, and MNC R&D centers (Qualcomm, Nvidia, Intel, AMD, Apple) are hiring ✅ Government-backed startups and access to EDA tools growing rapidly 💰 4. High Salaries & Career Growth ✅ VLSI engineers command top-tier pay due to niche skill demand ✅ Specializations like RTL Design, Verification, Physical Design, DFT, Analog Layout offer excellent upward mobility 🎓 5. Strong Training & Education Ecosystem ✅ IITs, IISc, IIITs & private universities offer focused MTech/PhD programs ✅ CDAC, SCL, ISRO, & private firms actively engage in internships & research ✅ Online platforms like NPTEL, ChipEdge, and IIT-M’s eMasters make upskilling easier than ever 🌍 6. Global Career Mobility ✅ VLSI skills are globally transferable ✅ Indian talent is in high demand in USA, Europe, Taiwan, South Korea, etc. ✅ Pro Tip for Aspiring VLSI Engineers: 📚 Build strong fundamentals: Digital Design, Verilog/SystemVerilog 🛠️ Get hands-on with tools like Cadence, Synopsys 🎯 Choose a specialization early (RTL, PD, Analog, Verification, DFT) 👨💼 Take up real-time projects or internships during BTech/MTech 2025 is not just the right time—it’s a historic opportunity to be part of India’s semiconductor revolution. #VLSIIndia #SemiconductorsIndia #ChipDesignIndia #MakeInIndia #IndiaSemiconductorMission #FablessIndia #HiringInIndia

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Analog vs. Digital Layout in VLSI Design – What Sets Them Apart? When it comes to chip design, layout is where theory meets silicon. While both analog and digital layouts aim to achieve functionality, their design philosophies differ drastically. 1. Nature of Signals Digital Layout: Deals with logic levels (0s and 1s). As long as timing and noise margins are satisfied, small variations don’t matter. Analog Layout: Sensitive to continuous signal variations. Even slight mismatches or parasitics can degrade performance. 2. Design Goals Digital → Maximize speed, density, and power efficiency. Analog → Ensure precision, matching, low noise, stability, and reliability. 3. Symmetry & Matching Digital: Focus on compactness and routing efficiency. Symmetry isn’t critical. Analog: Device matching (current mirrors, differential pairs, capacitors) is vital. Techniques like common-centroid and interdigitated layouts are used. 4. Sensitivity to Parasitics Digital: Parasitics matter mainly for timing (delay). Tools can optimize these automatically. Analog: Parasitics (capacitance, resistance, coupling) directly affect gain, bandwidth, and offset. Careful manual tuning is required. 5. Automation vs. Manual Effort Digital: Highly automated with P&R (Place & Route) tools. Designers focus more on RTL and synthesis. Analog: Still heavily manual, requiring deep circuit understanding + layout expertise. Tools assist, but human judgment is key. 6. Scaling with Technology Digital: Scales well with Moore’s Law. Shrinking nodes → faster & smaller chips. Analog: Scaling is tricky. Precision, voltage headroom, and device matching don’t always improve with smaller nodes. Digital layout is about automation, density, and speed, while analog layout is about art, precision, and intuition. Both are indispensable, but analog layout remains a craft that demands experience and meticulous attention to detail. 📩 Want to Master Analog Design? Apply here → https://lnkd.in/dZi8JDQA 📱 WhatsApp → https://lnkd.in/g9wNMycs 📡 Telegram → https://t.me/AnalogIC_RFIC #Semiconductor #VLSI #AnalogDesign #DigitalDesign #ChipDesign #ICLayout #Cadence #SemiconductorJobs #FutureOfWork #Electronics #MixedSignal

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Importance of Testcase in ASIC Verification in VLSI (Complete details with Categorization): A Testcase in any language is used to verify the functional correctness and the integrity of the design. Its basic functionality is to check whether the design is meeting its requirement as per the specification [1] Functional Tests --> In this type of test, the functionality or feature of an IP/module or a subsystem is verified a. Data transfer like read and write cycle, address and data phase, wait states. b. Protocol checks or feature specific to IP, FSM verification c. Command based training, sequence checks and Data Path checks d. Fault and error injection tests, calibration tests [2] Register-based Tests --> RW Tests, RO/WO Tests, Default Read/Hard reset Tests, Soft reset tests, Negative RO/WO Tests, Aliasing, Broadcasting, Special Register test. [3] Connectivity Tests [4] Clock and Reset Tests [5] Boot up Tests, wake up sequence, training sequence tests. For eg. In the case of DDR – MPC Training, RD DQ Calibration, Command Bus training, Write leveling, etc [6] Command and Sequence-based Tests. [7] Overlapping and Unallocated Region tests. [8] Back-to-back data transfer-based tests. [9] UPF Tests --> Power domain, Level Shifter, etc [10] Code Coverage Tests --> In this test toggle, expression, branch, FSM, and conditional coverage holes are measured, and depending on the holes, tests are being written to completely exercise the DUT [11] Functional Coverage Tests --> In these types of test categories, the functionality of DUT is being measured with the help of bins. There are several ways to do it. If there are coverage holes, more bins are coded to cover those areas, complex scenarios are covered with cross coverage. [12] Assertion checks --> Can be thought of as a check against the design. Basically, these are insertion points within the design which improve the observability and debugging ability. [13] C based test for processors and CPU. [14] GLS But to achieve all the above features, testcases are broadly classified into the following two types: [1] Directed Testcase: These are the scenarios that the verification engineers can think of or can anticipate. [2] RandomTestcase: These are the scenarios where the maximum amount of bugs can be caught. The random seeds will hit many different use cases which can not be anticipated earlier and has the probability to catch the design issues. Ideally, random tests can be classified into the following two categories: [1] Corner cases --> This is the bug that is only possible to catch when many different scenarios are processed together or they overlap and the best way to catch this type of scenario is to run more repeated regression with more seeds. [2] Stress testing -->These types of tests are useful to check the performance and the scalability of the DUT under multiple concurrent activities and unpredictable scenarios. #vlsi #asic #electronics #engineering

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Building APB Slave from scratch in verilog Building an APB slave can be done in two ways. Either you directly go to the ACCESS phase and perform read or write, or the other way is to detect the SETUP phase and decide whether to jump to the write or read state, where we cross-check whether we are getting the correct signal level for the ACCESS phase and then perform the update. The first approach only checks valid signal levels for the ACCESS phase, while the second approach verifies both SETUP & ACCESS phase signal levels. The first approach is used when we wish to build a slave that is always ready to serve the master request. Let us assume we are building an APB memory. In the reset state, we initialize memory locations to default values and keep pready low. As soon as reset is deasserted, we make pready high, conveying to the master that we are ready to serve a transaction. We then check the values of psel & penable every clock. As soon as we find both high, we know we are in the ACCESS phase. At this point, we check the value of pwrite. If it is high, we update the memory; else, we need to return data in the same clock tick. Since pready is already high, we cannot use a sequential always block (as we did with write operations). Instead, we use another always block (combinational) to immediately update the value of the prdata bus without waiting for the next clock tick. Again, we check the values of psel & penable, confirm both are high along with pwrite low, and then return data on the prdata bus. The second approach uses a two always-block FSM approach, where one always block detects the type of operation and signal values for valid SETUP & ACCESS phases, and then conveys ready when we jump to write or read. We start with the IDLE state and stay in IDLE as long as reset is asserted. Once reset is removed, we follow the state given by the next-state decoder. After removal of reset, we remain in the IDLE state waiting for a valid SETUP phase. As soon as we find psel = 1, we know we are in the SETUP phase. Based on the value of pwrite, we jump either to the WRITE or READ state. If pwrite is high, we jump to the WRITE state; else, we jump to the READ state. In WRITE, we wait until we find a valid ACCESS phase, i.e., when both psel & penable are high. As soon as we find both of them high, we make pready high (immediately due to the combinational always block). At the same time, the other always block performs the update in memory based on the type of operation. Now you can try interfacing both master and slave together and see how they behave. If you wish to learn building APB peripherals with us from scratch, give a try to this course: https://lnkd.in/gG-k9FCC

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Samsung Semiconductor India Research (SSIR) & VLSI System Design (VSD) Offer #FREE #VSDSquadron #FPGA Boards for #RISCV Learning in Karnataka High Schools! Your Child Can Design the Future. We're Giving Them the Tools. The next technological revolution will not be built in Silicon Valley. It will be built in Karnataka. The India Semiconductor Mission 2030 needs its architects. Not in a decade. Now. In an unprecedented move, Samsung Semiconductor India Research is partnering with VSD to launch a groundbreaking initiative: RISC-V on FPGA for High School. We are selecting 500 students from Karnataka to receive the VSDSquadron FPGA board at no cost. This is not a toy. It is a key to the future. Your child will not just use technology. They will create it. They will learn the language of innovation—RISC-V—and hold the power to shape it in their hands. This is where India's technological sovereignty begins. Not in a lab. At your kitchen table. The future is not something we enter. It is something we build. Let your child be a builder. https://lnkd.in/gZ3hDU6W RISC-V International India Semiconductor Mission India Electronics and Semiconductor Association VLSI Society of India (VSI) Ministry of Electronics and Information Technology Digital India RISC-V (DIR-V) Program Digital India Programme SEMI India SEMI Foundation

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