Moe Adham

Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. TT-Ascalon is Tenstorrent’s high-performance RISC-V CPU, built on open standards to provide maximum flexibility and architectural control. It is based on the open RISC-V ISA and is RVA23 compliant. A central focus of the Ashling–Tenstorrent collaboration is comprehensive trace support, built on the RISC-V standard N-Trace architecture. RiscFree integrates with Tenstorrent’s Ascalon CPUs to capture detailed trace data across multi-core systems, enabling real-time visibility into instruction execution, memory transactions, and key system events. In addition to N-Trace, Tenstorrent’s Debug Signal Trace (DST) infrastructure has been fully implemented in its Ascalon CPUs, providing access to critical micro-architectural signals alongside standard trace data during post-silicon validation. DST enhances debugging, performance analysis, and coverage, and is fully supported by Ashling’s RiscFree tools—enabling deep trace visibility with minimal integration overhead. Learn more here: https://lnkd.in/gthF_9uj #RISCVEverwhere #DEBUG #Tenstorrent

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🤝 STMicroelectronics and Morse Micro will be hosting a live joint webinar on 17 September 2025 on how to unlock #IoT 2.0 with Wi-Fi #HaLow and #STM32. 💡 In this webinar, ST and Morse Micro will deep dive into the MM6108-EKH05-05US, a powerful Wi-Fi HaLow (IEEE 802.11ah) development board purpose-built for a wide range of IoT applications. Combining Morse Micro’s #MM6108 Wi-Fi HaLow chip with ST’s advanced components, including the #STM32U5 ultra-low-power MCU, BlueNRG-M2 Bluetooth® module, and the #IIS328DQ 3-axis accelerometer, this development board is ready to power smart cities, industrial monitoring, building automation, and more. Key topics/learnings: ----------------------- 🌟 What defines IoT 2.0 and, more importantly, why traditional wireless tech is no longer enough 🌟 Why Wi-Fi HaLow is the key to long-range, high-throughput IoT 2.0 applications 🌟 ST's role is supporting next gen IoT development and platforming 🌟 How to get started with the MM6108-EKH05-05US dev board for rapid prototyping (whether you’re designing a next-gen asset tracker or a connected environmental sensor) 🌟 Application examples across industrial, smart building, and urban IoT use cases (e.g. camera) Register today via https://lnkd.in/gDksyUxq

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MAJOR ADVANCES IN (AI) TESTING DEMONSTRATED AT ECOC Exhibition 2025. I enjoyed a fascinating 3-way discussion about testing on the exhibition floor this week. Photonic integrated circuits operate at very high frequencies. We see InP and TFLN operating up to 110 GHz. Manufacturing is done at the wafer level, so we need to find partners who can test at such high frequencies, preferably automatically. In the video below, we discussed first with Lawrence van der Vegt, Head of Photonics at MPI Corporation. Founded in 1995 and headquartered in Hsinchu, Taiwan, MPI Corporation is a global technology leader in the testing of Semiconductors, Light Emitting Diodes, Photo Detectors, Lasers, Materials Research, and more. In September 2025, they announced the release of a fully integrated 250 GHz broadband test solution for the new Keysight Technologies NA5305A/7A PNA-X Frequency Extender. It builds on their deep expertise in sub-terahertz probing and on-wafer measurements. We explored why this is needed now. We also hear from Amir H. Ghadimi, CEO of Lightium based in Zurich, Switzerland. He explains what they need from an end-user perspective.  He also comments on a partnership between MPI Corporation and Axiomatic_AI. Design Engineer Mahdi Safari explains how their AI-driven SmartMeasure system utilises natural language to configure the probe station, select devices, and optimise the measurement order to maximise information retrieval. MPI tell me they have a lot of new developments on their roadmap to share at the OFC Conference 2026 and in Malaga next year. Onward to meet other Optica Corporate Members exhibiting this year and with a powerful deep-tech story to share! Does that apply to your company too? Join Optica and let's discuss.

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A compact, practical field-guide to CDC (Clock Domain Crossing)—what it is, why it bites, and proven design/verification patterns that actually work. What is CDC and why it’s hard When a signal produced by one clock domain is sampled by another unrelated (asynchronous/plesiochronous/mesochronous) clock, it can violate setup/hold at the receiving flop and enter metastability. You can’t eliminate metastability; you only reduce its probability to an acceptably low level and prevent bad fanout/glitches/reconvergence from turning one metastable event into many. Core concepts (quick glossary) • Asynchronous domains: No fixed phase/frequency relation. Needs full CDC handling. • Mesochronous: Same nominal frequency, unknown phase. Treat as async unless you have a guaranteed phase relationship. • Plesiochronous: Nearly same frequency but with drift. Treat as async. • Metastability parameters: τ (time constant of the receiving flop) and T₀ (device-dependent). • MTBF (mean time between failure): Roughly MTBF ≈ exp((Tres − T₀)/τ) / (Fclk · Ftoggle) Increase resolution time (extra sync stages), slow data toggle rate, or use faster flops to push MTBF >> product lifetime. What crossings exist (and what to use) 1. 1-bit level (slowly changing)- Metastability-2-flop (or 3-flop) synchronizer in destination clock 2. 1-bit pulse, src slower than dst- Pulse can be missed-2-flop + edge detect in dst, or stretch pulse in src 3. 1-bit pulse, src faster than dst-Pulse often missed-Toggle synchronizer or req/ack handshake 4.Multi-bit control (correlated bits)-Bit-skew; illegal combos-Encode to one-hot/Gray, or pass data + valid with handshake 5.Multi-bit data stream-Coherency & throughput-Asynchronous FIFO with Gray-coded pointers 6.Cross-domain resets-Deassertion metastability-Synchronous deassertion per domain; RDC checks 7. Source-synchronous buses-Skew, phase drift-Capture with forwarded clock, then re-sync to local clock 8.Cross-clock enables/gates-Glitch propagation-Generate enables locally after sync; avoid comb logic on CDC path Asynchronous FIFO (throughput workhorse) • Dual-clock RAM. • Write pointer (src clk) and read pointer (dst clk). • Convert binary pointers → Gray code before sending across; synchronize Gray pointers (2-flop) at the other side. • Empty/Full compare in the local domain using the remote pointer that has been Gray-synced. Timing & constraints (STA/SDC hygiene) • Declare async clocks: set_clock_groups -asynchronous -group {clk_src} -group {clk_dst} • Cut CDC data paths to avoid meaningless timing violations: set_false_path -from [get_clocks clk_src] -to [get_clocks clk_dst] • For multi-bit Gray buses (FIFO pointers), constrain skew so all bits arrive within <= one destination clock: • Use set_max_delay -datapath_only or set_bus_skew between pointer flop Qs (src) and sync inputs (dst). • Don’t put combinational logic between synchronizer stages. • Place the two synchronizer flops physically close (same cell row)

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