Synopsys Design compiler 学习笔记（收藏）

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Synopsys Design compiler 学习笔记

   design compiler流程

  Design compiler工作流程大致分为四步:

1)Load designs and libraries

   Dc的启动文件.synopsys_dc.setup:

# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#  Library Setup
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
set search_path "$search_path ../ref/db ./unmapped ./mapped ./scripts ./rtl ./.solutions"


set synthetic_library dw_foundation.sldb
set target_library   "sc_max.db"
set link_library     "* $target_library $synthetic_library"


echo "\n\nSettings:"
echo "search_path:       $search_path"
echo "link_library:      $link_library"
echo "target_library:    $target_library"
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#  Miscellaneous
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
suppress_message {LINT-1 LINT-28 LINT-32 LINT-33 UID-401}
history keep 200
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
#  Aliases
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
alias h history
alias rc "report_constraint -all_violators"
alias page_on {set sh_enable_page_mode true}
alias page_off {set sh_enable_page_mode false}
alias fr "remove_design -designs"
#  Use pre-compiled "alib" directory placed in user's home directory
#  instead of creating a new one - saves compile_ultra run-time
set alib_library_analysis_path ".."


echo "\n\nI am ready...\n"

DC运行：

read_verilog {A.v B.v TOP.v} 
current_design MY_TOP 
link
check_design
 


write –format ddc –hier –output unmapped/MY_TOP.ddc

1

参考学习笔记

Tcl与Design Compiler （1） —DC综合与Tcl语法结构概述

Tcl与Design Compiler （2）—DC综合的流程

Tcl与Design Compiler （3）—DC启动环境的设置

Tcl与Design Compiler （4）—综合库（时序库）和DC的设计对象

2)Apply design constranints

###################################
# Constraints file for design
###################################




create_clock [get_ports clk] -period 2.1
set_clock_uncertainty -setup 0.1 [get_clocks clk]
set_clock_transition 0.05 [get_clocks clk]




# Using default "Operating Conditions"  and automatic Wire Load Selection
# from the "slow corner" library: cb13fs120_tsmc_max




set_input_delay -clock clk  -max 0.2 [get_ports "a2 b* c* d*"]




set_input_delay -max 1.9 -clock clk [get_ports a1]




set_input_delay -clock clk  -max 0.05 [get_ports M]
set_input_delay -clock clk  -max 0.2 [get_ports X]
set_input_delay -clock clk  -max 0.3 [get_ports N]




set_input_delay -clock clk  -max 0.1 [get_ports sel1]
set_input_delay -clock clk  -max 1.0 [get_ports sel2]
set_driving_cell -lib_cell inv0d1 [all_inputs]
remove_driving_cell [get_ports clk]




set_output_delay -clock clk  -max 0.2 [all_outputs]
set_load 0.5 [all_outputs]
set_max_area 1600

DC运行：

source TOP.con
check_timing

2

参考学习笔记

Tcl与Design Compiler （5）—基本的时序路径约束

Tcl与Design Compiler （6）——环境、设计规则和面积约束

Tcl与Design Compiler （7）——DC的逻辑综合与优化

Tcl与Design Compiler （8）——综合后的形式验证

3)Synthesize the design

compile –boundary –scan –map
report_constraint –all_violators

3

参考学习笔记

Tcl与Design Compiler （9）——其他的时序约束选项（一）

Tcl与Design Compiler （10）——其他的时序约束选项（二）

4）Write out design data

write –f verilog –hier –out mpd/TOP.v 
write –f ddc –hier –out mpd/TOP.ddc
exit

4

参考学习笔记

Tcl与Design Compiler （11）——综合后处理

Tcl与Design Compiler （12）——Design Compliler中常用到的命令（示例）总结