Richard Lum

UBM (Under Bump Metallization) Purpose: UBM is a critical layer in advanced semiconductor packaging, enabling reliable electrical and mechanical connections between the chip and solder bumps or copper pillars. Functions: Provides electrical interconnection, wetting for solder, diffusion barrier, and mechanical support. Prevents failures like delamination, solder voids, and electromigration. Applications: Used in Flip-Chip, Wafer-Level Packaging (WLP), Fan-Out WLP, 2.5D/3D IC stacking, and high-end 3D packaging (e.g., HBM, CoWoS). Materials: Multi-layer stacks: adhesion (Ti, TiW, Ta), seed/conductor (Cu), barrier (TiN, Ta, Ni), wetting (Au, Ag), and solder (Sn, SnAgCu). Etching: Selective etchants are used for each metal layer (e.g., HF+H₂O₂ for Ti, H₃PO₄+H₂O₂ for Cu, KI/I₂ for Au). Process control is crucial to avoid over-etching and ensure pad accuracy. Trends: Moving toward finer pitches (<50 μm), eco-friendly chemistries, cost reduction (less Au), and dry/plasma etching for better precision. Conclusion: UBM is foundational for next-gen semiconductor reliability, yield, and performance, especially as packaging becomes more complex and dense.

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🇦🇸 ASEAN’s Semiconductor Moment: From Assembly to Strategy Semiconductors are the new oil — powering everything from AI and cars to defence and digital economies. The global chip market is projected to grow from US$600 billion in 2024 to nearly US$980 billion by 2029. The new ASEAN Framework for Integrated Semiconductor Supply Chain (AFISS) aims to change that trajectory. It’s the region’s first attempt to align national strengths into a cohesive semiconductor strategy — one that treats diversity as an advantage. 🧩 Each country has a role to play: 🔹 Malaysia — advanced packaging and test 🔹 Vietnam — assembly and component hubs 🔹 Philippines — IC design and R&D 🔹 Singapore — logistics and innovation leadership The goal is clear: 👉 From fragmented strengths to a resilient regional ecosystem 👉 From low-value positions to strategic autonomy 👉 From competition to collaboration The policy brief outlines six strategic thrusts for ASEAN’s semiconductor future: 1️⃣ Infrastructure 2️⃣ Technology innovation & transfer 3️⃣ Supply chain hubs 4️⃣ Policy reform 5️⃣ Market access 6️⃣ Talent development This is how ASEAN can move upstream — into design, fabrication, and advanced R&D — while remaining a neutral, trusted hub in global supply chains. If ASEAN gets this right, it could anchor a trillion-dollar industry — not just as a production base, but as a strategic partner in global resilience. I share semiconductor insights everyday. Follow me 👉 Andrew Chan Yik Hong for actionable perspectives on policy, strategy & industry shifts and ring the bell 🔔 to get notified whenever I post. 💬 If this post resonates with you, re-post, drop a comment or leave a like — I’d love to hear your thoughts.

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🤝 STMicroelectronics and Morse Micro will be hosting a live joint webinar on 17 September 2025 on how to unlock #IoT 2.0 with Wi-Fi #HaLow and #STM32. 💡 In this webinar, ST and Morse Micro will deep dive into the MM6108-EKH05-05US, a powerful Wi-Fi HaLow (IEEE 802.11ah) development board purpose-built for a wide range of IoT applications. Combining Morse Micro’s #MM6108 Wi-Fi HaLow chip with ST’s advanced components, including the #STM32U5 ultra-low-power MCU, BlueNRG-M2 Bluetooth® module, and the #IIS328DQ 3-axis accelerometer, this development board is ready to power smart cities, industrial monitoring, building automation, and more. Key topics/learnings: ----------------------- 🌟 What defines IoT 2.0 and, more importantly, why traditional wireless tech is no longer enough 🌟 Why Wi-Fi HaLow is the key to long-range, high-throughput IoT 2.0 applications 🌟 ST's role is supporting next gen IoT development and platforming 🌟 How to get started with the MM6108-EKH05-05US dev board for rapid prototyping (whether you’re designing a next-gen asset tracker or a connected environmental sensor) 🌟 Application examples across industrial, smart building, and urban IoT use cases (e.g. camera) Register today via https://lnkd.in/gDksyUxq

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The Fab Whisperer: The Most Misleading Metric in Fabs Every fab runs on metrics: OEE, cycle time, line yield, on-time delivery, cost per wafer/layer. But there’s one metric that, more often than not, misleads fabs into thinking they’re winning when in reality they’re falling behind: “Utilization”. Why it matters? On the surface, utilization feels like the right goal: keep tools busy, maximize output. But fabs are not simple factories — they’re complex, interconnected systems with bottlenecks and long cycle times. When fabs chase utilization too hard, it usually leads to: WIP bloats — tools run wafers just to look “busy,” flooding the downstream line with lots. Cycle time explosion — bottlenecks starve while non-bottlenecks overproduce. False sense of efficiency — high utilization ≠ high throughput. Technician overload — more setups, more firefighting. The paradox is that the harder a fab pushes utilization, the slower and more expensive it often gets. From the field: I once worked with a fab proudly reporting 95% utilization on bottleneck tools. Management celebrated. But wafer cycle times were climbing, and customers were missing deliveries. Tracing WIP revealed that the implant area was flooding the downstream Litho bottlenecks. Lots piled up in front of scanners, miss-managing critical recipes' priorities and inflating cycle time by weeks. Litho Utilization looked world-class. Actual fab delivery performance was collapsing. When we shifted the focus to throughput at the bottleneck and WIP turns at non-bottlenecks, cycle time improved 18% in just three months, and on-time delivery jumped from 70% to 93%. The fix: Stop chasing utilization as a headline fab metric. Focus on throughput at the bottleneck — the true limiter of output. Use metrics for bottleneck tools such as % Idle with WIP, throughput/tool/day or per shift. Focus on Dynamic Cycle Time (DCT) and WIP turns on non-bottlenecks — they reveal the hidden cost of overproduction. Align fab scheduling with pull principles wherever possible. Focus on FLOW. Teach fab leaders the difference between “busy” and “productive.” The most misleading metric isn’t the one you ignore. It’s the one you celebrate — while it quietly erodes flow. So… drop a comment if in your fab the focus on keeping tools busy trumps delivering wafers on time. What's your most misleading metric? #TheFabWhisperer #Semiconductor #FabOperations #Metrics #Utilization #CycleTime #ManufacturingExcellence

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High bandwidth memory (HBM) production capacity is expected to reach 400K units by the end of 2024, according to DIGITIMES Asia. This kind of growth introduces new and more complex technological challenges, making investment in R&D more important than ever. Today’s breakthroughs are built on years of forward-thinking research, iteration, and engineering expertise. Continuous R&D investment is needed from both the public and industry stakeholders to continue the march towards next-generation technologies like #HBM4, which meets the memory density, performance, and yield demands of #AI and #HPC. We see this daily in our work on advanced materials development - MST was born from years of sustained R&D, aimed at improving performance and yields across advanced nodes. DIGITIMES gives a great look at what this process looks like for HBM today: https://bit.ly/4ghB7vy

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