Search Results for "eda" - Page 2
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Showing 682 open source projects for "eda"
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Kactus2
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at... -
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This project provides a analog / mixed signal IC schematic capture and layout tool with the accompanying netlisters, simulators, and verification tools.
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VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
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SPI via FTDI
Control electronic devices using most popular protocols.
Application allows make connection to electronic devices using popular interfaces (SPI, I2C, 1-Wire, uWire, UART) and control them trough FTDI ICs (FT2232D, FT2232H, FT4232H, FT232H etc). The title was formed historically and no longer reflects the functionality of the app. This software works in Windows 7-11 with .NET 4.5. -
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PEDA is electronic design automation software for schematic and PCB design with unique tools selection stack for manual routing and unified PCB and schematic database developed in Qt5 library.
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IEC 60870-5 104 Protocol download
IEC 104 RTU Server Client Simulator Source Code Library Win Linux
v21.06.012 Complete implementation of iec 104 protocol standard including File transfer. Make your RTU, protocol converter, Gateway, HMI, Data concentrator compatible with iec 104. *Industry Proved * Worldwide Customers Download Evaluation Kit - IEC 104 Development Bundle In the Development Bundle, We included IEC 104 Server & Client Simulator, Windows & Linux... -
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PCB is a tool for the layout of printed circuit boards. PCB can produce industry standard RS-274X and Excellon NC-Drill format output for submission to board manufacturers.
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Open-source interpreted Verilog simulator with a feature set and performance similar to Verilog-XL. Implements all IEEE 1364-1995 features along with some Verilog-2001 features. Full support for Verilog PLIs.
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Proximus for Ryzen AI
Runtime extension of Proximus enabling Deployment on AMD Ryzen™ AI
This project extends the Proximus development environment to support deployment of AI workloads on next-generation AMD Ryzen™ AI processors, such as the Ryzen™ AI 7 PRO 7840U featured in the Lenovo ThinkPad T14s Gen 4 ,one of the first true AI PCs with an onboard Neural Processing Unit (NPU) capable of 16 TOPS (trillion operations per second). Originally designed for use with Windows 11 Pro, this runtime was further enhanced to work under Linux environments, allowing developers and... -
Connect every part of your business to one bank accountNorth One is proudly built for small businesses, startups and freelancers across America. Make payments easily, keep tabs on your money and put your finances on autopilot through smart integrations with the tools you’re already using. North One was built to make managing money easy so you can focus on running your business. No more branches. No more lines. No more paperwork. Get complete access to your North One Account from your phone or computer, wherever your business takes you. Create Envelopes for taxes, payroll, rent, and anything else automatically.
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1. flattenverilog : Flattens the specified verilog module by removing the hierarchies. It works both for RTL and netlist. 2. preprocessverilog : Verilog Preprocessor to resolve macros like nested `ifdef , `define 3. createhierarchy : Verilog Hierarchy Creation Tool to group a list of instances in RTL or enlist. This creates a new wrapper by encapsulating the instance 4. flatteninstances : Flattens the given list of hierarchical instances- this removes hierarchy by pulling the...
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Eng-DB-2 is a light-weight engineering database. It allows to manage components/assemblies and their associated AVLs and technical documentation, assemble BOMs for finished goods and annotate these with quotations received from suppliers.
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Baya - SoC Integration Platform
Best in class SoC Integration Platform, IP-XACT, Verilog VHDL, UPF
1. Comes with 200+ high level Tcl commands around SoC platform assembly 2. Easy to start - use the verilog2baya tool to convert existing SoC/SS into Baya 3. Adhoc and Interface based connections 4. Autoconnections 5. Rule based connections between component ports 6. A variety of SoC integration Methodologies 6.a. XLS/CSV Based connections 6.b. Port-to-Port Adhoc connections 6.c. IP-XACT and System Verilog Interface based connections 6.d. ... 7. Maintains a connectivity... -
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Free Parsers for Liberty UPF SDC VCD
Free Liberty, UPF, SDC and VCD Parsers with Python, Java and Tcl APIs
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eavref
A tool for low-power CMOS voltage reference designs
EAVREF is a computer-aided tool for robustly designing ultra-low-power CMOS voltage references. The tool is compatible with the powerful Ngspice simulator, enabling open-source microelectronics design flow with SkyWater 130nm Technology. -
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System Verilog Parser IEEE 1800 LRM
IEEE LRM compliant System Verilog Parser in Java with Python, Tcl API
This parser has been developed to help users to implement their Verilog tool/utility on the top this library. It reads RTL and populates its internal data structures. There are APIs to extract the design information from the database, there are APIs to elaborate every element of the design along with basic expression evaluation capabilities. It has been bundled as an executable JAR file along with a sample application which reads a RTL file(s), elaborates and dumps it back to show the... -
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LaSolv
Solves symbolic electrical AC circuit equations
In electrical engineering, AC circuits are often used in the design process. However, deriving the gain, input impedance or what have you is tedious and error prone. LaSolv takes a SPICE like description of your circuit and solves for whatever parameter you specify- voltage gain, trans-impedance, input impedance, etc. -
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NetworkDesigner does the design of various impedance matching networks. The designs are useful for both solid state designs as well as vacuum tube/valve circuits. In the newest version, the filter design functionality has been split off and will appear as a separate app. This makes for a cleaner user interface, The latest version was made from the FOX toolkit, and it is included in the package. This is the latest stable version of FOX.
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A portable loudspeaker design system supporting measurement, modeling, simulation and optimization of boxes, filters and systems.
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jCLS
The Component Library Sorcerer
WARNING: This project is under hard development and not intended for productive use yet but only for discussion. jCLS helps to create and maintain fine detailed component libraries for EDA tools like Altium Designer. It provides tools for data generation for masses of single parts from only the most necessary informations. Having good maintained and rich described and voluptuous detailed component libraries needs normally masses of time, work and discipline. jCLS comes here to save you from... -
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Turns-n-Layers is a command line transformer and induction coil design aid that calculates the amount of wire needed, both length (feet) and weight (lbs). Also, the finished dimensions of the coil and the resistance are also returned.
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PyAMS
PyAMS (Python for Analog and Mixed Signals) CAD approach
PyAMS (Python for Analog and Mixed Signals) is used to simplify modeling analog elements and simulate electronic circuit The objectives of PyAMS is: - Drawing circuit by schematic (CAD approach); - Simulating the circuit; - Creating new symbols for models; - Creating new models of electrical elements by using Python language with pyams_lib; - Presenting simulation results in waveform or in probe; - PyAMS is developed with Python 3+, ElectronJS and NodeJs - Licensed under:... -
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EDAUtils Converters
Free converters across IP-XACT Verilog VHDL Liberty SystemC
verilog2vhdl : Tool to convert Verilog into VHDL by keeping the same structure and function for ease of correlation. vhdl2verilog : Tool to convert VHDL into Verilog by keeping the same structure and function for ease of correlation verilog2ipxact :Tool to create IP-XACT Component or Design from a Verilog Module. ipxact2verilog : Tool to convert IP-XACT into Verilog module ipxactinterface2svinterface : Converts IP-XACT Bus Definition / BusInterface into System Verilog... -
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Free VHDL Parser with Java, Python and T
IEEE VHDL-93 LRM supported parser implemented in Java, APIs Python/Tcl
This parser has been developed for those who wants to develop his/her own tool around VHDL RTL. Only synthesizable subset of VHDL is supported and it may not work for machine/tool generated VHDL files. This parser has been developed in Java in order to make it platform independent. It reads RTL and populates its internal object model. There are APIs to extract the design information from the database, APIs to elaborate the design along with expression evaluation capabilities. This tool has... -
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CircuiTikZ Generator
This software is a tool for designing electronic circuits using LaTeX.
This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library.
