yyy@wxsc08:~/Vitis-Tutorials/Getting_Started/Vitis/example/u200/hw_emu$ sh ./run.sh INFO: Found Xilinx Platform INFO: Loading 'vadd.xclbin' INFO: [HW-EMU 05] Path of the simulation directory : /home/yyy/Vitis-Tutorials/Getting_Started/Vitis/example/u200/hw_emu/.run/84241/hw_em/device0/binary_0/behav_waveform/xsim ERROR: [SDx-EM 08-0] Failed to connect to device process

时间: 2025-04-06 09:16:14 AIGC 浏览: 86
<think>好的,我现在需要帮助用户解决在Vitis硬件仿真过程中遇到的“Sdx-em 08-0 error failed to connect to device process”错误。首先,我要理解这个错误的具体情况。根据用户提到的错误信息,连接设备进程失败,这可能涉及到硬件配置、仿真环境设置或软件版本兼容性问题。 首先,我应该回顾相关的引用内容,看看有没有相关的解决方案。用户提供的引用中有几个涉及硬件和驱动的问题,比如引用[4]提到了USB-OTG的GPIO测试,这可能与硬件连接有关,但不确定是否直接相关。引用[2]提到hostapd_cli连接问题,可能涉及进程通信,但环境不同。引用[3]中的固件加载错误虽然不影响IPA工作,但固件问题有时会导致意外错误,不过这里用户的问题是关于连接设备进程失败,可能需要检查仿真环境的固件或驱动是否正确加载。 接下来,我需要系统地分析可能导致这个错误的原因。常见的可能包括: 1. **硬件仿真环境配置错误**:比如Vitis的仿真设置不正确,或者目标设备配置有误。 2. **驱动程序或固件问题**:设备驱动未正确安装,或者固件版本不兼容。 3. **进程通信问题**:仿真工具与设备进程之间的通信被防火墙或权限设置阻止。 4. **软件版本不兼容**:使用的Vitis版本与硬件设计或操作系统不兼容。 5. **端口占用或资源冲突**:其他程序占用了仿真所需的端口或资源。 然后,我需要根据这些可能性逐步提供解决方案。例如: - **检查仿真配置**:确认Vitis项目中硬件仿真设置是否正确,目标设备是否选择正确,仿真脚本是否有错误。 - **验证驱动和固件**:确保相关设备的驱动程序已正确安装,并且固件版本与仿真工具兼容。引用[4]中提到USB_ID和OTG_PWR_EN的检测,虽然具体环境不同,但可以类比检查硬件检测信号是否正常。 - **权限和防火墙设置**:在Linux环境下,可能需要root权限运行仿真工具,或者调整防火墙设置允许相关通信。 - **更新或重新安装工具**:如果软件版本过旧,可能存在已知的bug,更新到最新版本或应用补丁可能解决问题。 - **检查日志文件**:查看Vitis生成的仿真日志,寻找更详细的错误信息,帮助定位问题根源。 此外,用户提供的引用[3]提到固件加载错误不影响IPA工作,但在这里可能需要确认仿真所需的固件是否存在或路径是否正确。例如,检查是否有类似“ipa_fws.elf”文件缺失的情况,尽管错误提示不同,但方法类似。 在提供步骤时,应该结构清晰,逐步引导用户排查问题。同时,需要确保用户理解每个步骤的目的,例如检查配置、验证驱动、查看日志等。可能还需要提醒用户注意操作系统权限,如使用sudo命令运行工具,或者检查环境变量设置是否正确。 最后,生成相关问题,帮助用户进一步解决可能遇到的关联问题,比如性能分析、优化方法或其他常见错误处理。</think>### 逐步解决方案 针对Vitis硬件仿真中出现的**"Sdx-em 08-0 error failed to connect to device process"**错误,请按以下步骤排查: 1. **验证硬件仿真环境配置** - 检查Vitis工程设置中的目标设备型号是否与硬件设计(如FPGA型号)匹配。 - 确认硬件仿真脚本(如`launch_hw_emu`命令参数)是否包含正确的设备路径和仿真模式(例如`-g`调试模式)。 - 尝试重新生成仿真文件(如`xsct`脚本重新编译硬件描述文件)。 2. **检查设备驱动与固件** - 确保仿真目标设备(如Zynq系列)的驱动已正确安装,参考厂商文档更新驱动[^4]。 - 若使用USB-OTG等外设接口,验证GPIO信号(如`USB_ID`和`OTG_PWR_EN`)是否在仿真中被正确模拟[^4]。 - 检查仿真环境是否加载了正确的固件文件(类似引用[3]中的`.elf`文件缺失问题)。 3. **排查进程通信问题** - 在Linux系统中,使用`netstat -tulnp`检查仿真工具所需端口(如TCP 3121)是否被占用。 - 临时关闭防火墙或安全软件:`sudo ufw disable`(Ubuntu)。 - 以管理员权限运行Vitis:`sudo vitis`(避免权限不足导致进程间通信失败)。 4. **验证工具版本兼容性** - 确认Vitis版本与操作系统、硬件设计文件(如XSA文件)兼容。 - 更新Vitis至最新补丁(已知旧版本存在仿真进程管理bug)。 5. **分析仿真日志** - 查看Vitis生成的`hw_emu`目录下的日志文件(如`simulate.log`),搜索`ERROR`或`failed`字段。 - 示例关键日志线索: ``` [ERROR] Device process exited prematurely (code 127) [DEBUG] Failed to bind to socket port 3121: Address already in use ``` --- ### 典型解决方案案例 若日志显示端口冲突: ```bash # 终止占用端口的进程 sudo lsof -i :3121 sudo kill -9 <PID> # 重新启动硬件仿真 launch_hw_emu -g -forward-port 3121 ``` ---
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Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 17:03:51 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../../src/SmoothProfileOnXAxisMean.cpp in debug mode csim.mk:85: recipe for target 'obj/SmoothProfileOnXAxisMean.o' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 ../../../../src/SmoothProfileOnXAxisMean.cpp: In function 'void SmoothProfileOnXAxisMean(hls::stream<float>&, hls::stream<float>&, ap_uint<6>, float)': ../../../../src/SmoothProfileOnXAxisMean.cpp:246:37: error: operands to ?: have different types 'int' and 'ap_int_base<6, false>::RType<32, true>::plus {aka ap_int<33>}' read_ptr = (read_ptr == 32) ? 0 : read_ptr + 1; ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ ../../../../src/SmoothProfileOnXAxisMean.cpp:246:37: note: and each type can be converted to the other ../../../../src/SmoothProfileOnXAxisMean.cpp:249:35: error: operands to ?: have different types 'int' and 'ap_int_base<6, false>::RType<32, true>::plus {aka ap_int<33>}' write_ptr = (write_ptr == 32) ? 0 : write_ptr + 1; ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~ ../../../../src/SmoothProfileOnXAxisMean.cpp:249:35: note: and each type can be converted to the other make: *** [obj/SmoothProfileOnXAxisMean.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 1.236 seconds; current allocated memory: 0.398 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 1 seconds. Total elapsed time: 2.984 seconds; peak allocated memory: 199.363 MB. Finished C simulation.

Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 15:29:28 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean.cpp WARNING: [HLS 200-40] Cannot find design file 'SmoothProfileOnXAxisMean.cpp' INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h INFO: [HLS 200-10] Adding design file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h' to the project INFO: [HLS 200-1510] Running: add_files -tb SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution solution2 -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0.35ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1464] Running solution command: config_export -display_name=SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -format=ip_catalog INFO: [HLS 200-1464] Running solution command: config_export -library=KU060_200M_II1_NoGray_WIN33_250721 INFO: [HLS 200-1464] Running solution command: config_export -output=D:/HLS/SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -rtl=verilog INFO: [HLS 200-1464] Running solution command: config_export -vendor=WEIGUO INFO: [HLS 200-1464] Running solution command: config_export -version=2.5 INFO: [HLS 200-1464] Running solution command: config_cosim -tool=xsim INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: config_export -display_name SmoothProfileOnXAxisMean -format ip_catalog -library KU060_200M_II1_NoGray_WIN33_250721 -output D:/HLS/SmoothProfileOnXAxisMean -rtl verilog -vendor WEIGUO -version 2.5 INFO: [HLS 200-1510] Running: config_cosim -tool xsim INFO: [HLS 200-1510] Running: set_clock_uncertainty 0.35 INFO: [HLS 200-1510] Running: source ./SmoothProfileOnXAxisMean_NoGray/solution2/directives.tcl INFO: [HLS 200-1510] Running: set_directive_top -name SmoothProfileOnXAxisMean SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Generating csim.exe Makefile.rules:317: recipe for target 'csim.exe' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 obj/SmoothProfileOnXAxisMean_test.o: In function main': G:\vitis2023_project\SmoothProfileOnXAxisMean_NoGray\solution2\csim\build/../../../src/SmoothProfileOnXAxisMean_test.cpp:59: undefined reference to SmoothProfileOnXAxisMean(hls::stream<float, 0>&, hls::stream<float, 0>&, ap_uint<6>, float)' collect2.exe: error: ld returned 1 exit status make: *** [csim.exe] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 2.536 seconds; current allocated memory: 0.371 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 4.239 seconds; peak allocated memory: 199.672 MB. Finished C simulation.

ny@wxsc07:~/new/dxp_test_bak - new$ make clean && make CFLAGS="-g" rm -f main.o src/generate_box_pairs.so src/info_partition.so src/output_bin.so src/get_org_info.so src/generate_box_pairs.o src/info_partition.o src/output_bin.o src/get_org_info.o dxp_test mpic++ -I ./include -I /tools/Xilinx/Vitis_HLS/2022.2/include/ -O3 -fPIC -c main.cpp -o main.o In file included from ./include/md_fix.h:5, from main.cpp:7: ./include/ppip_float.h:7: warning: "__always_inline" redefined 7 | #define __always_inline //__attribute__((always_inline)) inline | In file included from /usr/include/features.h:461, from /usr/include/x86_64-linux-gnu/bits/libc-header-start.h:33, from /usr/include/stdio.h:27, from main.cpp:1: /usr/include/x86_64-linux-gnu/sys/cdefs.h:319: note: this is the location of the previous definition 319 | # define __always_inline __inline __attribute__ ((__always_inline__)) | mpic++ -I ./include -I /tools/Xilinx/Vitis_HLS/2022.2/include/ -O3 -fPIC -c src/generate_box_pairs.cpp -o src/generate_box_pairs.o In file included from ./include/md_fix.h:5, from src/generate_box_pairs.cpp:1: ./include/ppip_float.h:7: warning: "__always_inline" redefined 7 | #define __always_inline //__attribute__((always_inline)) inline | In file included from /usr/include/features.h:461, from /usr/include/x86_64-linux-gnu/c++/9/bits/os_defines.h:39, from /usr/include/x86_64-linux-gnu/c++/9/bits/c++config.h:528, from /usr/include/c++/9/bits/stl_algobase.h:59, from /usr/include/c++/9/deque:60, from /usr/include/c++/9/queue:60, from /tools/Xilinx/Vitis_HLS/2022.2/include/hls_stream.h:23, from ./include/md_fix.h:4, from src/generate_box_pairs.cpp:1: /usr/include/x86_64-linux-gnu/sys/cdefs.h:319: note: this is the location of the previous definition 31

Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 25 19:09:15 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMeanOpt INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanFixed.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanFixed.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanOpt.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanOpt.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanOptimize.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanOptimize.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: source ./SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/directives.tcl INFO: [HLS 200-1510] Running: set_directive_top -name SmoothProfileOnXAxisMeanOpt SmoothProfileOnXAxisMeanOpt INFO: [HLS 200-1510] Running: csim_design -clean -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries ERROR: [SIM 211-107] error deleting "G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim/build\test_0_win1.csv": permission denied ERROR: [SIM 211-100] CSim failed with errors. INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 1 seconds. Elapsed time: 0.144 seconds; current allocated memory: 0.090 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 2 seconds. Total CPU system time: 1 seconds. Total elapsed time: 2.422 seconds; peak allocated memory: 199.145 MB. Finished C simulation.

root@ubuntu22:~/Desktop/FPGA/ip_filter# v++ -c -t hw --platform xilinx_u50_gen3x16_xdma_5_202210_1 --kernel ip_filter -I. -o ip_filter.xo ip_filter.cpp Option Map File Used: '/tools/Xilinx/Vitis/2024.1/data/vitis/vpp/optMap.xml' ****** v++ v2024.1 (64-bit) **** SW Build 5074859 on 2024-05-20-23:21:20 **** Start of session at: Wed Jul 23 01:39:57 2025 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved. ERROR: [v++ 60-602] Source file does not exist: /root/Desktop/FPGA/ip_filter/ip_filter.cpp ERROR: [v++ 60-602] Source file does not exist: /root/Desktop/FPGA/ip_filter/ip_filter.cpp INFO: [v++ 60-1662] Stopping dispatch session having empty uuid. INFO: [v++ 60-1653] Closing dispatch client. root@ubuntu22:~/Desktop/FPGA/ip_filter# ls build logs v++_ip_filter_381047.backup.log v++_ip_filter_491942.backup.log CMakeLists.txt src v++_ip_filter_381314.backup.log v++_ip_filter_595831.backup.log compile_commands.json UserConfig.cmake v++_ip_filter_381753.backup.log v++_ip_filter_698387.backup.log _ide v++_ip_filter_166092.backup.log v++_ip_filter_382018.backup.log v++_ip_filter.log ip_filter.ltx v++_ip_filter_166450.backup.log v++_ip_filter_382341.backup.log vitis-comp.json ip_filter.xclbin v++_ip_filter_166567.backup.log v++_ip_filter_382656.backup.log _x ip_filter.xclbin.info v++_ip_filter_166972.backup.log v++_ip_filter_38574.backup.log xcd.log ip_filter.xclbin.link_summary v++_ip_filter_273588.backup.log v++_ip_filter_38865.backup.log ip_filter.xo v++_ip_filter_273752.backup.log v++_ip_filter_39353.backup.log ip_filter.xo.compile_summary v++_ip_filter_274098.backup.log v++_ip_filter_491629.backup.log root@ubuntu22:~/Desktop/FPGA/ip_filter# ls src host.cpp ip_filter.cpp

INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 25 14:22:55 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMeanOpt INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanFixed.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanFixed.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanOpt.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanOpt.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Compiling ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp in debug mode csim.mk:97: recipe for target 'obj/SmoothProfileOnXAxisMeanOpt.o' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean_test.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean_test.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp: In function 'void SmoothProfileOnXAxisMeanOpt(hls::stream<float>&, hls::stream<float>&, ap_uint<6>, float)': ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:41:28: error: 'i' was not declared in this scope bool data_available = (i < 3200); ^ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:48:9: error: continue statement not within a loop continue; ^~~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:52:9: error: continue statement not within a loop continue; ^~~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: error: ambiguous overload for 'operator*' (operand types are 'ap_fixed_base<18, 5, true, (ap_q_mode)5u, (ap_o_mode)3u, 0>::RType<24, 11, true>::minus {aka ap_fixed<25, 12, (ap_q_mode)5u, (ap_o_mode)3u, 0>}' and 'float') fixed_t compensation = (sum - avg * valid_count) * 0.01f; ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long double, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(double, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(float, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(unsigned int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long unsigned int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(ap_ulong {aka long long unsigned int}, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(ap_slong {aka long long int}, float) <built-in> In file included from D:/vitis202302/Vitis_HLS/2023.2/include/ap_fixed.h:10:0, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:360, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, ap_ulong) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, false>::mult = ap_fixed<89, 76, (ap_q_mode)5u, (ap_o_mode)3u, 0>; ap_ulong = long long unsigned int] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2383:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, ap_slong) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, true>::mult = ap_fixed<89, 76, (ap_q_mode)5u, (ap_o_mode)3u, 0>; ap_slong = long long int] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2382:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, long unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, false>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2381:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned long, _AP_SIZE_long, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, long int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, true>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2380:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(long, _AP_SIZE_long, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, false>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2379:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned int, _AP_SIZE_int, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, true>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2378:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(int, _AP_SIZE_int, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, short unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, false>::mult = ap_fixed<41, 28, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2377:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned short, _AP_SIZE_short, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, short int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, true>::mult = ap_fixed<41, 28, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2376:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(short, _AP_SIZE_short, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, unsigned char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, false>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2375:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned char, 8, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, signed char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, true>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2374:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(signed char, 8, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, CHAR_IS_SIGNED>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, CHAR_IS_SIGNED>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2373:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(char, 8, CHAR_IS_SIGNED) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<1, 1, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, bool) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<1, 1, false>::mult = ap_fixed<26, 13, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2372:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(bool, 1, false) ^~~~~~~~~~~~~~~~~~ make: *** [obj/SmoothProfileOnXAxisMeanOpt.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 3.165 seconds; current allocated memory: 0.410 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 1 seconds. Total elapsed time: 5.2 seconds; peak allocated memory: 199.391 MB. Finished C simulation.

'Invoking: ARM v7 gcc linker' arm-none-eabi-gcc -mcpu=cortex-a9 -mfpu=vfpv3 -mfloat-abi=hard -Wl,-build-id=none -specs=Xilinx.spec -Wl,-T -Wl,../src/lscript.ld -LD:/vitiswork2024.1/system_wrapper/export/system_wrapper/sw/system_wrapper/standalone_ps7_cortexa9_0/bsplib/lib -o "qspi_Flash_test.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group d:/xilinx2024.1/vitis/2024.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/ld.exe: ./src/main.o: in function QspiFlashPolledExample': D:\vitiswork2024.1\qspi_Flash_test\Debug/../src/main.c:92: undefined reference to FlashReadID' d:/xilinx2024.1/vitis/2024.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/ld.exe: D:\vitiswork2024.1\qspi_Flash_test\Debug/../src/main.c:94: undefined reference to FlashQuadEnable' d:/xilinx2024.1/vitis/2024.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/ld.exe: D:\vitiswork2024.1\qspi_Flash_test\Debug/../src/main.c:96: undefined reference to FlashErase' d:/xilinx2024.1/vitis/2024.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/ld.exe: D:\vitiswork2024.1\qspi_Flash_test\Debug/../src/main.c:99: undefined reference to FlashWrite' d:/xilinx2024.1/vitis/2024.1/gnu/aarch32/nt/gcc-arm-none-eabi/x86_64-oesdk-mingw32/usr/bin/arm-xilinx-eabi/../../libexec/arm-xilinx-eabi/gcc/arm-xilinx-eabi/12.2.0/ld.exe: D:\vitiswork2024.1\qspi_Flash_test\Debug/../src/main.c:103: undefined reference to FlashRead' collect2.exe: error: ld returned 1 exit status make[1]: *** [makefile:43: qspi_Flash_test.elf] Error 1 make: *** [makefile:34: all] Error 2

Starting C synthesis ... Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:31 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl' INFO: [HLS 200-1510] Running: source G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl INFO: [HLS 200-1510] Running: open_project axi_test INFO: [HLS 200-10] Opening project 'G:/HLS_Test/axi_test/axi_test'. INFO: [HLS 200-1510] Running: add_files axi_interfaces.c INFO: [HLS 200-10] Adding design file 'axi_interfaces.c' to the project INFO: [HLS 200-1510] Running: add_files -tb axi_interfaces_test.c INFO: [HLS 200-10] Adding test bench file 'axi_interfaces_test.c' to the project INFO: [HLS 200-1510] Running: open_solution axi_test -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/HLS_Test/axi_test/axi_test/axi_test'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcvu11p-flga2577-1-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcvu11p-flga2577-1-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling(apcc) ../../../../axi_interfaces_test.c in debug mode INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/apcc.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:34 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test/axi_test/axi_test/csim/build' ../../../../axi_interfaces_test.c:42:10: warning: implicit declaration of function 'system' is invalid in C99 [-Wimplicit-function-declaration] retval = system("diff --brief -w result.dat result.golden.dat"); ^ 1 warning generated. ../../../../axi_interfaces_test.c:42:10: warning: implicit declaration of function 'system' is invalid in C99 [-Wimplicit-function-declaration] retval = system("diff --brief -w result.dat result.golden.dat"); ^ 1 warning generated. INFO: [APCC 202-3] Tmp directory is G:/HLS_Test/axi_test/axi_test/axi_test/csim/build/apcc_db_HP/231284131701203 INFO: [APCC 202-1] APCC is done. INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 0.741 seconds; peak allocated memory: 8.262 MB. Compiling(apcc) ../../../../axi_interfaces.c in debug mode INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/apcc.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 18 15:20:36 +0800 2025 INFO: [HLS 200-10] In directory 'G:/HLS_Test/axi_test/axi_test/axi_test/csim/build' INFO: [APCC 202-3] Tmp directory is G:/HLS_Test/axi_test/axi_test/axi_test/csim/build/apcc_db_HP/81684133866848 INFO: [APCC 202-1] APCC is done. INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 0.722 seconds; peak allocated memory: 11.082 MB. Generating csim.exe diff: result.golden.dat: No such file or directory Test failed !!! @E Simulation failed: Function 'main' returns nonzero value '1'. ERROR: [SIM 211-100] 'csim_design' failed: nonzero return value. INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 5.089 seconds; current allocated memory: 0.633 MB. 4 while executing "source G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl" invoked from within "hls::main G:/HLS_Test/axi_test/axi_test/axi_test/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 2 seconds. Total CPU system time: 0 seconds. Total elapsed time: 7.19 seconds; peak allocated memory: 193.797 MB. Finished C simulation.

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