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vitis hlsで float型をIEEE754の32bitの生bit(sp_uint<32>)にcastしたいです。 vitis hls 2021.1なのでhls::bit_castは使えません

时间: 2025-08-28 11:55:17 AIGC 浏览: 9
<think> 我们面临的问题:在Vitis HLS 2021.1环境中,将float类型转换为IEEE754标准的32位二进制表示(即sp_uint<32>类型),但不能使用hls::bit_cast。 分析: IEEE754标准的单精度浮点数(float)在内存中占据32位。我们需要获取这32位的二进制表示。 在C/C++中,通常可以通过指针操作或联合体(union)来实现类型转换而不改变位模式。但在HLS中,由于硬件设计的特殊性,我们需要考虑可综合性和安全性。 解决方案: 1. 使用联合体(union):定义一个包含float和uint32_t(或等效的无符号整数类型)的联合体,通过写入float成员然后读取整数成员来获取位表示。 2. 使用指针操作:将float的地址转换为uint32_t的指针,然后解引用获取值(注意:这可能导致对齐问题,但在大多数平台上安全,且HLS通常允许)。 注意:Vitis HLS中,我们可以使用ap_uint<32>(或sp_uint<32>,根据上下文,可能是同一个东西)来表示32位无符号整数。 然而,在HLS环境中,我们需要注意: - 联合体方法在C++中虽然是常见的,但根据标准,通过一个成员写入然后从另一个成员读取是未定义行为(UB),尽管大多数编译器支持。 - 指针转换的方法同样依赖于实现定义的行为,但在HLS中通常可以工作。 由于Vitis HLS基于C++,并且通常支持这些低级操作,我们可以选择其中一种方法。 另外,我们还可以使用内存复制(memcpy)的方式,这是C++20之前没有bit_cast时的标准做法,且不会产生未定义行为。 步骤: - 使用memcpy,将float的每个字节复制到一个uint32_t变量中。 - 由于HLS支持标准库,我们可以包含<cstring>头文件使用memcpy。 推荐方法:使用memcpy,因为它是安全且可移植的。 具体步骤: 1. 定义一个float变量,假设为f。 2. 定义一个ap_uint<32>(或unsigned int,但为了精确位宽,建议用ap_uint<32>)变量作为输出。 3. 使用memcpy,将float的地址开始的4字节数据复制到ap_uint<32>变量的内存中。 注意:由于HLS需要可综合,memcpy会被综合为线连接(wire),不会产生实际的复制操作,因此是零开销。 代码示例: #include <cstring> // 或者使用string.h,但c++推荐cstring ap_uint<32> float_to_bits(float f) { ap_uint<32> bits; memcpy(&bits, &f, sizeof(float)); return bits; } 注意:确保float为32位(IEEE754单精度),ap_uint<32>也是32位。 在Vitis HLS中,ap_uint<32>与unsigned int都是32位,但ap_uint是一个更安全的位精确类型。 另外,也可以使用联合体,但需要确保联合体定义正确: union float_union { float f; ap_uint<32> u; }; ap_uint<32> float_to_bits(float f) { float_union fu; fu.f = f; return fu.u; } 两种方法在HLS中应该都能工作。但memcpy方法更符合标准,且没有未定义行为的担忧。 根据引用[3]中提到的,我们在Vitis HLS中创建项目并设置Top Function,然后可以将上述函数作为HLS模块的一部分。 然而,注意:在HLS中,我们通常需要指定接口和协议等,但对于内部转换操作,以上函数可以在内部使用。 结论:建议使用memcpy方法。 下面给出一个完整的示例,包括函数定义和测试(如果需要测试台,可以在测试台中调用)。 示例代码: #include <cstring> #include <ap_int.h> ap_uint<32> float_to_bits(float f) { ap_uint<32> bits; // 使用memcpy将浮点数的位模式复制到ap_uint变量 std::memcpy(&bits, &f, sizeof(float)); // 或者使用:memcpy(&bits, &f, sizeof(float)); 如果不使用std命名空间 return bits; } 注意:在HLS项目中,需要包含ap_int.h头文件以使用ap_uint类型。 如果项目中还没有包含ap_int.h,请添加。 另外,如果使用Vitis HLS 2021.1,确保设置正确的C++标准(例如C++11或更高),因为memcpy在C++中是标准库的一部分。 测试:可以在测试台中调用该函数,传入一个浮点数,然后打印出转换后的32位十六进制或二进制,与IEEE754标准对比。 例如: 输入:1.0 -> 应该得到0x3f800000 (二进制:00111111100000000000000000000000) 相关问题: 1. 为什么在HLS中不能使用hls::bit_cast? 2. 在HLS中使用memcpy进行位转换会有性能开销吗? 3. 除了float,其他数据类型(如double)如何进行类似的位转换? 4. 在HLS中,如何将ap_uint<32>转换回float? </think> 在 Vitis HLS 2021.1 中,若无法使用 `hls::bit_cast` 将 `float` 转换为 IEEE 754 标准的 32 位 `ap_uint<32>`,可通过以下两种安全可靠的解决方案实现: --- ### 方法 1:使用联合体(Union)实现类型双关 ```cpp #include <ap_int.h> ap_uint<32> float_to_ieee754(float f) { union { float f_val; ap_uint<32> u_val; } converter; converter.f_val = f; // 写入 float 值 return converter.u_val; // 读取二进制位表示 } ``` **原理**: 联合体共享内存空间,通过写入 `float` 成员后读取 `ap_uint<32>` 成员,直接获取 IEEE 754 位模式(需确保 `sizeof(float)==4`)。 --- ### 方法 2:使用内存复制(`memcpy`) ```cpp #include <ap_int.h> #include <cstring> // 必需头文件 ap_uint<32> float_to_ieee754(float f) { ap_uint<32> bits; // 将 float 的 4 字节内存拷贝到 ap_uint<32> std::memcpy(&bits, &f, sizeof(float)); return bits; } ``` **优势**: - 严格遵循 C++ 标准,无未定义行为风险 - 在 HLS 综合中零开销(仅映射为硬件连线) --- ### 关键注意事项 1. **平台兼容性**: 两种方法均要求 `float` 为 IEEE 754 单精度(32 位),Vitis HLS 默认满足此条件[^3]。 2. **综合安全性**: Vitis HLS 支持联合体和 `memcpy` 的综合(综合后为直接位映射,无额外逻辑)[^1][^3]。 3. **性能对比**: | 方法 | 资源消耗 | 延迟周期 | 代码可移植性 | |------------|----------|----------|--------------| | 联合体 | 零 | 零 | 依赖编译器 | | `memcpy` | 零 | 零 | 标准 C++ | --- ### 验证示例 ```cpp // 测试用例 (testbench) #include <iostream> int main() { float f = -0.75f; // IEEE 754: 0xBF400000 ap_uint<32> bits = float_to_ieee754(f); std::cout << "Hex: 0x" << std::hex << bits << std::endl; return 0; } // 预期输出:Hex: 0xBF400000 ``` --- ### 相关问题 1. 如何在 Vitis HLS 中将 `ap_uint<32>` 转换回 `float` 类型? 2. 若目标平台不支持 IEEE 754 标准,如何进行安全的浮点转换? 3. Vitis HLS 中有哪些其他方法处理非标准数据类型的位操作? [^1]: 控制报告的产生:在硬件模拟阶段,我们可以通过v++ -R &lt;report_level&gt;控制报告上的内容。 [^3]: HLS即High level Synthesis,高层次综合,简单来说就是用C++写硬件代码。
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INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Fri Jul 25 14:22:55 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMeanOpt INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanFixed.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanFixed.cpp' to the project INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMeanOpt.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMeanOpt.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Compiling ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp in debug mode csim.mk:97: recipe for target 'obj/SmoothProfileOnXAxisMeanOpt.o' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean_test.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean_test.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp: In function 'void SmoothProfileOnXAxisMeanOpt(hls::stream<float>&, hls::stream<float>&, ap_uint<6>, float)': ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:41:28: error: 'i' was not declared in this scope bool data_available = (i < 3200); ^ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:48:9: error: continue statement not within a loop continue; ^~~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:52:9: error: continue statement not within a loop continue; ^~~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: error: ambiguous overload for 'operator*' (operand types are 'ap_fixed_base<18, 5, true, (ap_q_mode)5u, (ap_o_mode)3u, 0>::RType<24, 11, true>::minus {aka ap_fixed<25, 12, (ap_q_mode)5u, (ap_o_mode)3u, 0>}' and 'float') fixed_t compensation = (sum - avg * valid_count) * 0.01f; ~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~ ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long double, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(double, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(float, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(unsigned int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(long unsigned int, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(ap_ulong {aka long long unsigned int}, float) <built-in> ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:73:62: note: candidate: operator*(ap_slong {aka long long int}, float) <built-in> In file included from D:/vitis202302/Vitis_HLS/2023.2/include/ap_fixed.h:10:0, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:360, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMeanOpt.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, ap_ulong) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, false>::mult = ap_fixed<89, 76, (ap_q_mode)5u, (ap_o_mode)3u, 0>; ap_ulong = long long unsigned int] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2383:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(ap_ulong, _AP_SIZE_ap_slong, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, ap_slong) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_ap_slong, _AP_SIZE_ap_slong, true>::mult = ap_fixed<89, 76, (ap_q_mode)5u, (ap_o_mode)3u, 0>; ap_slong = long long int] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2382:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(ap_slong, _AP_SIZE_ap_slong, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, long unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, false>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2381:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned long, _AP_SIZE_long, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, long int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_long, _AP_SIZE_long, true>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2380:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(long, _AP_SIZE_long, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, false>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2379:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned int, _AP_SIZE_int, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_int, _AP_SIZE_int, true>::mult = ap_fixed<57, 44, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2378:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(int, _AP_SIZE_int, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, short unsigned int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, false>::mult = ap_fixed<41, 28, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2377:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned short, _AP_SIZE_short, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, short int) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<_AP_SIZE_short, _AP_SIZE_short, true>::mult = ap_fixed<41, 28, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2376:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(short, _AP_SIZE_short, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, unsigned char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, false>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2375:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(unsigned char, 8, false) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, true>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, signed char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, true>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2374:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(signed char, 8, true) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, CHAR_IS_SIGNED>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, char) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<8, 8, CHAR_IS_SIGNED>::mult = ap_fixed<33, 20, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2373:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(char, 8, CHAR_IS_SIGNED) ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2293:3: note: candidate: typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<1, 1, false>::mult operator*(const ap_fixed_base<_AP_W, _AP_I, _AP_S, _AP_Q, _AP_O, _AP_N>&, bool) [with int _AP_W = 25; int _AP_I = 12; bool _AP_S = true; ap_q_mode _AP_Q = (ap_q_mode)5u; ap_o_mode _AP_O = (ap_o_mode)3u; int _AP_N = 0; typename ap_fixed_base<_AP_W, _AP_I, _AP_S>::RType<1, 1, false>::mult = ap_fixed<26, 13, (ap_q_mode)5u, (ap_o_mode)3u, 0>] operator BIN_OP( \ ^ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2347:3: note: in expansion of macro 'AF_BIN_OP_WITH_INT' AF_BIN_OP_WITH_INT(*, C_TYPE, (BITS), (SIGN), mult) \ ^~~~~~~~~~~~~~~~~~ D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_fixed_base.h:2372:1: note: in expansion of macro 'ALL_AF_OP_WITH_INT' ALL_AF_OP_WITH_INT(bool, 1, false) ^~~~~~~~~~~~~~~~~~ make: *** [obj/SmoothProfileOnXAxisMeanOpt.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 3.165 seconds; current allocated memory: 0.410 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 1 seconds. Total elapsed time: 5.2 seconds; peak allocated memory: 199.391 MB. Finished C simulation.

INFO: [HLS 214-291] Loop 'VITIS_LOOP_56_2' is marked as complete unroll implied by the pipeline pragma (src/SmoothProfileOnXAxisMeanOptimize.cpp:56:19) INFO: [HLS 214-291] Loop 'VITIS_LOOP_43_1' is marked as complete unroll implied by the pipeline pragma (src/SmoothProfileOnXAxisMeanOptimize.cpp:43:19) INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_56_2' (src/SmoothProfileOnXAxisMeanOptimize.cpp:56:19) in function 'SmoothProfileOnXAxisMeanOptimize' completely with a factor of 11 (src/SmoothProfileOnXAxisMeanOptimize.cpp:15:0) INFO: [HLS 214-186] Unrolling loop 'VITIS_LOOP_43_1' (src/SmoothProfileOnXAxisMeanOptimize.cpp:43:19) in function 'SmoothProfileOnXAxisMeanOptimize' completely with a factor of 32 (src/SmoothProfileOnXAxisMeanOptimize.cpp:15:0) INFO: [HLS 214-248] Applying array_partition to '_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6buffer': Complete partitioning on dimension 1. (src/SmoothProfileOnXAxisMeanOptimize.cpp:24:0) INFO: [HLS 214-248] Applying array_partition to '_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE3win': Complete partitioning on dimension 1. (src/SmoothProfileOnXAxisMeanOptimize.cpp:27:0) INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 6.958 seconds; current allocated memory: 202.637 MB. INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.002 seconds; current allocated memory: 202.637 MB. INFO: [HLS 200-10] Starting code transformations ... INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.051 seconds; current allocated memory: 208.652 MB. INFO: [HLS 200-10] Checking synthesizability ... WARNING: [SYNCHK 200-23] src/SmoothProfileOnXAxisMeanOptimize.cpp:100: variable-indexed range selection may cause suboptimal QoR. INFO: [SYNCHK 200-10] 0 error(s), 1 warning(s). INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.06 seconds; current allocated memory: 210.320 MB. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (src/SmoothProfileOnXAxisMeanOptimize.cpp:16:9) to (src/SmoothProfileOnXAxisMeanOptimize.cpp:90:9) in function 'SmoothProfileOnXAxisMeanOptimize'... converting 13 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (src/SmoothProfileOnXAxisMeanOptimize.cpp:94:45) in function 'SmoothProfileOnXAxisMeanOptimize'... converting 7 basic blocks. INFO: [XFORM 203-401] Performing if-conversion on hyperblock from (src/SmoothProfileOnXAxisMeanOptimize.cpp:89:13) to (src/SmoothProfileOnXAxisMeanOptimize.cpp:101:1) in function 'SmoothProfileOnXAxisMeanOptimize'... converting 10 basic blocks. INFO: [XFORM 203-11] Balancing expressions in function 'SmoothProfileOnXAxisMeanOptimize' (src/SmoothProfileOnXAxisMeanOptimize.cpp:10:1)...20 expression(s) balanced. INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.157 seconds; current allocated memory: 233.824 MB. INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.088 seconds; current allocated memory: 233.828 MB. INFO: [HLS 200-10] Starting hardware synthesis ... INFO: [HLS 200-10] Synthesizing 'SmoothProfileOnXAxisMeanOptimize' ... INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-42] -- Implementing module 'SmoothProfileOnXAxisMeanOptimize' INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [SCHED 204-11] Starting scheduling ... INFO: [SCHED 204-61] Pipelining function 'SmoothProfileOnXAxisMeanOptimize'. INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 81, function 'SmoothProfileOnXAxisMeanOptimize' INFO: [SCHED 204-11] Finished scheduling. INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.319 seconds; current allocated memory: 238.062 MB. INFO: [BIND 205-100] Starting micro-architecture generation ... INFO: [BIND 205-101] Performing variable lifetime analysis. INFO: [BIND 205-101] Exploring resource sharing. INFO: [BIND 205-101] Binding ... INFO: [BIND 205-100] Finished micro-architecture generation. INFO: [HLS 200-111] Finished Binding: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.118 seconds; current allocated memory: 239.660 MB. INFO: [HLS 200-10] ---------------------------------------------------------------- INFO: [HLS 200-10] -- Generating RTL for module 'SmoothProfileOnXAxisMeanOptimize' INFO: [HLS 200-10] ---------------------------------------------------------------- WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low. INFO: [RTGEN 206-500] Setting interface mode on port 'SmoothProfileOnXAxisMeanOptimize/points_in_z' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'SmoothProfileOnXAxisMeanOptimize/smoothed_z' to 'axis' (register, both mode). INFO: [RTGEN 206-500] Setting interface mode on port 'SmoothProfileOnXAxisMeanOptimize/mean_win_size' to 'ap_none'. INFO: [RTGEN 206-500] Setting interface mode on port 'SmoothProfileOnXAxisMeanOptimize/invalid_z' to 'ap_none'. INFO: [RTGEN 206-500] Setting interface mode on function 'SmoothProfileOnXAxisMeanOptimize' to 'ap_ctrl_none'. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_1' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_2' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_3' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_4' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_5' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_6' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_7' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_8' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_9' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_10' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_11' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_12' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_13' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_14' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_15' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_16' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_17' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_18' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_19' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_20' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE6bu_21' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_1' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_2' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_3' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_4' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_5' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_6' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_7' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_8' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_buffer_9' is power-on initialization. WARNING: [RTGEN 206-101] Register 'p_ZZ32SmoothProfileOnXAxisMeanOptimizeRN3hls6streamIfLi0EEES2_7ap_uintILi6EEfE3wi' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_19' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_8' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_5' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_4' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_3' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_2' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_1' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_0' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_18' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_17' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_16' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_15' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_14' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_13' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_12' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_11' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_10' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_9' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_7' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_hls_stream_float_0_hls_stream_float_0_ap_uint_6_float_wi_s_6' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_1' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_2' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_3' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_4' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_5' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_6' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_7' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_8' is power-on initialization. WARNING: [RTGEN 206-101] Register 'SmoothProfileOnXAxisMeanOptimize_stream_stream_ap_uint_6_float_win_9' is power-on initialization. INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'SmoothProfileOnXAxisMeanOptimize' pipeline 'SmoothProfileOnXAxisMeanOptimize' pipeline type 'function pipeline' INFO: [HLS 200-1552] Enabling free running pipeline (frp) architecture on pipeline 'SmoothProfileOnXAxisMeanOptimize' in module 'SmoothProfileOnXAxisMeanOptimize'. Estimated max control fanout for pipeline is 10267. WARNING: [RTGEN 206-101] Port 'SmoothProfileOnXAxisMeanOptimize/mean_win_size' has no fanin or fanout and is left dangling. Please use C simulation to confirm this function argument can be read from or written to. INFO: [RTGEN 206-100] Generating core module 'ddiv_64ns_64ns_64_59_no_dsp_1': 1 instance(s).

Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 17:03:51 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files src/SmoothProfileOnXAxisMean.cpp INFO: [HLS 200-10] Adding design file 'src/SmoothProfileOnXAxisMean.cpp' to the project INFO: [HLS 200-1510] Running: add_files -tb src/SmoothProfileOnXAxisMean_test.cpp INFO: [HLS 200-10] Adding test bench file 'src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution SmoothProfileOnXAxisMean_NoGray -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../../src/SmoothProfileOnXAxisMean.cpp in debug mode csim.mk:85: recipe for target 'obj/SmoothProfileOnXAxisMean.o' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../../src/SmoothProfileOnXAxisMean.cpp:1: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 ../../../../src/SmoothProfileOnXAxisMean.cpp: In function 'void SmoothProfileOnXAxisMean(hls::stream<float>&, hls::stream<float>&, ap_uint<6>, float)': ../../../../src/SmoothProfileOnXAxisMean.cpp:246:37: error: operands to ?: have different types 'int' and 'ap_int_base<6, false>::RType<32, true>::plus {aka ap_int<33>}' read_ptr = (read_ptr == 32) ? 0 : read_ptr + 1; ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~ ../../../../src/SmoothProfileOnXAxisMean.cpp:246:37: note: and each type can be converted to the other ../../../../src/SmoothProfileOnXAxisMean.cpp:249:35: error: operands to ?: have different types 'int' and 'ap_int_base<6, false>::RType<32, true>::plus {aka ap_int<33>}' write_ptr = (write_ptr == 32) ? 0 : write_ptr + 1; ~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~ ../../../../src/SmoothProfileOnXAxisMean.cpp:249:35: note: and each type can be converted to the other make: *** [obj/SmoothProfileOnXAxisMean.o] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 1.236 seconds; current allocated memory: 0.398 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray_liangjing/SmoothProfileOnXAxisMean_NoGray/SmoothProfileOnXAxisMean_NoGray/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 1 seconds. Total elapsed time: 2.984 seconds; peak allocated memory: 199.363 MB. Finished C simulation.

这是我的主机程序#include <iostream> #include <xrt/xrt_bo.h> #include <xrt/xrt_device.h> #include <xrt/xrt_kernel.h> int main() { try { // 1. 初始化设备 auto device = xrt::device(0); std::cout << "Device initialized" << std::endl; // 2. 加载xclbin auto uuid = device.load_xclbin("ip_filter.xclbin"); std::cout << "XCLBIN loaded with UUID: " << uuid.to_string() << std::endl; // 3. 创建内核对象 auto kernel = xrt::kernel(device, uuid, "ip_filter"); // 4. 准备测试数据 uint32_t test_ips[] = {0xC0A80101}; // 192.168.1.1 uint32_t test_rules[] = {0xC0A80100}; // 192.168.1.0/24 // 5. 创建缓冲区 auto ip_buf = xrt::bo(device, sizeof(test_ips), kernel.group_id(0)); auto rule_buf = xrt::bo(device, sizeof(test_rules), kernel.group_id(1)); auto out_buf = xrt::bo(device, sizeof(uint32_t), kernel.group_id(2)); // 6. 数据传输与执行 ip_buf.write(test_ips); rule_buf.write(test_rules); auto run = kernel(ip_buf, rule_buf, out_buf); run.wait(); // 7. 读取结果 out_buf.sync(XCL_BO_SYNC_BO_FROM_DEVICE); auto result = out_buf.map<uint32_t>(); std::cout << "Test result: " << (*result ? "MATCH" : "NO MATCH") << std::endl; } catch (const std::exception& e) { std::cerr << "Error: " << e.what() << std::endl; return 1; } return 0; }这是我的内核程序#include "ap_int.h" #include <cstdint> void ip_filter( uint32_t* input_ips, uint32_t* rules, uint32_t* output, uint32_t ip_count, uint32_t rule_count ) { #pragma HLS INTERFACE m_axi port=input_ips #pragma HLS INTERFACE m_axi port=rules #pragma HLS INTERFACE m_axi port=output output[0] = (input_ips[0] & 0xFFFFFF00) == rules[0] ? 1 : 0; }这是反馈root@ubuntu22:~/Desktop/FPGA/ip_filter# ./build/ip_filter Device initialized XCLBIN loaded with UUID: 9660bfcb-66b5-97b5-ecc3-1d037b2826c7 Filtered IP count: 1

Starting C simulation ... D:/vitis202302/Vitis_HLS/2023.2/bin/vitis_hls.bat G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-10] Running 'D:/vitis202302/Vitis_HLS/2023.2/bin/unwrapped/win64.o/vitis_hls.exe' INFO: [HLS 200-10] For user 'HP' on host 'desktop-qjs3vb7' (Windows NT_amd64 version 6.2) on Tue Jul 22 15:29:28 +0800 2025 INFO: [HLS 200-10] In directory 'G:/vitis2023_project' INFO: [HLS 200-2053] The vitis_hls executable is being deprecated. Consider using vitis-run --mode hls --tcl Sourcing Tcl script 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl' INFO: [HLS 200-1510] Running: source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl INFO: [HLS 200-1510] Running: open_project SmoothProfileOnXAxisMean_NoGray INFO: [HLS 200-10] Opening project 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray'. INFO: [HLS 200-1510] Running: set_top SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean.cpp WARNING: [HLS 200-40] Cannot find design file 'SmoothProfileOnXAxisMean.cpp' INFO: [HLS 200-1510] Running: add_files SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h INFO: [HLS 200-10] Adding design file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean.h' to the project INFO: [HLS 200-1510] Running: add_files -tb SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp -cflags -Wno-unknown-pragmas INFO: [HLS 200-10] Adding test bench file 'SmoothProfileOnXAxisMean_NoGray/src/SmoothProfileOnXAxisMean_test.cpp' to the project INFO: [HLS 200-1510] Running: open_solution solution2 -flow_target vivado INFO: [HLS 200-10] Opening solution 'G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2'. INFO: [SYN 201-201] Setting up clock 'default' with a period of 5ns. INFO: [SYN 201-201] Setting up clock 'default' with an uncertainty of 0.35ns. INFO: [HLS 200-1611] Setting target device to 'xcku060-ffva1156-2-e' INFO: [HLS 200-1505] Using flow_target 'vivado' Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2023.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html INFO: [HLS 200-1464] Running solution command: config_export -display_name=SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -format=ip_catalog INFO: [HLS 200-1464] Running solution command: config_export -library=KU060_200M_II1_NoGray_WIN33_250721 INFO: [HLS 200-1464] Running solution command: config_export -output=D:/HLS/SmoothProfileOnXAxisMean INFO: [HLS 200-1464] Running solution command: config_export -rtl=verilog INFO: [HLS 200-1464] Running solution command: config_export -vendor=WEIGUO INFO: [HLS 200-1464] Running solution command: config_export -version=2.5 INFO: [HLS 200-1464] Running solution command: config_cosim -tool=xsim INFO: [HLS 200-1510] Running: set_part xcku060-ffva1156-2-e INFO: [HLS 200-1510] Running: create_clock -period 5 -name default INFO: [HLS 200-1510] Running: config_export -display_name SmoothProfileOnXAxisMean -format ip_catalog -library KU060_200M_II1_NoGray_WIN33_250721 -output D:/HLS/SmoothProfileOnXAxisMean -rtl verilog -vendor WEIGUO -version 2.5 INFO: [HLS 200-1510] Running: config_cosim -tool xsim INFO: [HLS 200-1510] Running: set_clock_uncertainty 0.35 INFO: [HLS 200-1510] Running: source ./SmoothProfileOnXAxisMean_NoGray/solution2/directives.tcl INFO: [HLS 200-1510] Running: set_directive_top -name SmoothProfileOnXAxisMean SmoothProfileOnXAxisMean INFO: [HLS 200-1510] Running: csim_design -quiet INFO: [SIM 211-2] *************** CSIM start *************** INFO: [SIM 211-4] CSIM will launch GCC as the compiler. INFO: [HLS 200-2036] Building debug C Simulation binaries Compiling ../../../src/SmoothProfileOnXAxisMean_test.cpp in debug mode Generating csim.exe Makefile.rules:317: recipe for target 'csim.exe' failed In file included from D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:150:0, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/gmp.h:58:0: warning: "__GMP_LIBGMP_DLL" redefined #define __GMP_LIBGMP_DLL 0 In file included from D:/vitis202302/Vitis_HLS/2023.2/include/hls_fpo.h:140:0, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/hls_half_fpo.h:19, from D:/vitis202302/Vitis_HLS/2023.2/include/hls_half.h:26, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_private.h:52, from D:/vitis202302/Vitis_HLS/2023.2/include/etc/ap_common.h:666, from D:/vitis202302/Vitis_HLS/2023.2/include/ap_int.h:10, from ../../../src/SmoothProfileOnXAxisMean.h:3, from ../../../src/SmoothProfileOnXAxisMean_test.cpp:3: D:/vitis202302/Vitis_HLS/2023.2/include/floating_point_v7_1_bitacc_cmodel.h:142:0: note: this is the location of the previous definition #define __GMP_LIBGMP_DLL 1 obj/SmoothProfileOnXAxisMean_test.o: In function main': G:\vitis2023_project\SmoothProfileOnXAxisMean_NoGray\solution2\csim\build/../../../src/SmoothProfileOnXAxisMean_test.cpp:59: undefined reference to SmoothProfileOnXAxisMean(hls::stream<float, 0>&, hls::stream<float, 0>&, ap_uint<6>, float)' collect2.exe: error: ld returned 1 exit status make: *** [csim.exe] Error 1 ERROR: [SIM 211-100] 'csim_design' failed: compilation error(s). INFO: [SIM 211-3] *************** CSIM finish *************** INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 2.536 seconds; current allocated memory: 0.371 MB. 4 while executing "source G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" invoked from within "hls::main G:/vitis2023_project/SmoothProfileOnXAxisMean_NoGray/solution2/csim.tcl" ("uplevel" body line 1) invoked from within "uplevel 1 hls::main {*}$newargs" (procedure "hls_proc" line 16) invoked from within "hls_proc [info nameofexecutable] $argv" INFO: [HLS 200-112] Total CPU user time: 1 seconds. Total CPU system time: 0 seconds. Total elapsed time: 4.239 seconds; peak allocated memory: 199.672 MB. Finished C simulation.

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