zynq fixed_io

### Zynq Fixed IO Configuration and Usage In the context of configuring and using fixed IO on a Zynq device, several key aspects need attention. The peripheral I/O pins are typically pre-configured within the hardware design phase for most boards[^2]. This setup ensures that essential peripherals like UART can function correctly without additional configuration changes. For detailed configuration related specifically to USB functionality through Device Tree bindings, certain properties must be set appropriately. For instance: - `phy_type`: Specifies the type of PHY connected to the core (options include "utmi", "utmi_wide", "ulpi", "serial", or "hsic"). Setting this property is crucial as it influences how the PORTSC register operates. - `dr_mode`: Defines whether the mode should operate as "host", "peripheral", or "otg". If not specified, it defaults to "otg"[^3]. When working with Zynq's fixed IOs, these settings ensure proper communication between external devices and internal components via standardized interfaces such as UART or USB. #### Example Code Snippet for Configuring UART Output in Vivado HLS To illustrate setting up UART output which often relies on fixed IO configurations provided by default: ```c++ #include <hls_stream.h> void uart_output(hls::stream<int>& input_data){ int data; while (!input_data.empty()){ data = input_data.read(); // Assuming predefined UART interface exists here send_uart(data); } } ``` This example assumes an existing UART interface where sending data occurs over predefined connections established during board initialization.