I/O Interface (Interrupt and DMA Mode)

The method that is used to transfer information between internal storage and external I/O devices is known as I/O interface. The CPU is interfaced using special communication links by the peripherals connected to any computer system. These communication links are used to resolve the differences between CPU and peripheral.

Note: There exists special hardware components between CPU and peripherals to supervise and synchronize all the input and output transfers that are called interface units.

Mode of Transfer

The binary information that is received from an external device is usually stored in the memory unit. CPU merely processes the information but the source and target is always the memory unit. Data transfer between CPU and the I/O devices may be done in different modes:

1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).

Programmed I/O

• In this each data item transfer is initiated by an instruction in the program
• Usually the transfer is from a CPU register and memory. In this case it requires constant monitoring by the CPU of the peripheral devices.
• In this case, the I/O device does not have direct access to the memory unit. A transfer from I/O device to memory requires the execution of several instructions by the CPU
• Including an input instruction to transfer the data from device to the CPU and store instruction to transfer the data from CPU to memory.

Note: The CPU stays in the program loop until the I/O unit indicates that it is ready for data transfer. This keeps the CPU busy & can be avoided by using an interrupt facility.

Interrupt-Initiated I/O

Since in the above case we saw the CPU is kept busy unnecessarily. This situation can very well be avoided by using an interrupt driven method for data transfer. By using interrupt facility and special commands to inform the interface to issue an interrupt request signal whenever data is available from any device.

Steps:

• In the meantime the CPU can proceed for any other program execution.
• The interface meanwhile keeps monitoring the device.
• Whenever it is determined that the device is ready for data transfer it initiates an interrupt request signal to the computer.
• Upon detection of an external interrupt signal the CPU stops momentarily the task that it was already performing, branches to the service program to process the I/O transfer and then return to the task it was originally performing.
• The I/O transfer rate is limited by the speed with which the processor can test and service a device.
• The processor is tied up in managing an I/O transfer; a number of instructions must be executed for each I/O transfer.

Types of Interrupts:

• Hardware and Software Interrupts: Hardware interrupts are triggered by hardware pins from external devices, while software interrupts are generated by executing specific instructions in a program when required.
• Vectored and Non-Vectored Interrupts: Vectored interrupts use a static vector address assigned by the system, whereas non-vectored interrupts use a dynamic vector address determined at runtime.
• Maskable and Non-Maskable Interrupts: Maskable interrupts can be explicitly enabled or disabled by the system, while non-maskable interrupts are always enabled and cannot be disabled (e.g., for critical events like power failure).
• External and Internal Interrupts: External interrupts are generated by external hardware devices such as I/O peripherals, while internal interrupts are generated by the processor itself, e.g., due to power failure or illegal instructions.
• Synchronous and Asynchronous Interrupts: Synchronous interrupts occur at fixed time intervals in a controlled manner, whereas asynchronous interrupts are triggered unpredictably based on external events or instruction feedback.

Direct Memory Access

The data transfer between a fast storage media such as magnetic disk and memory unit is limited by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses, removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access.

• During DMA the CPU is idle and it has no control over the memory buses.
• The DMA controller takes over the buses to manage the transfer directly between the I/O devices and the memory unit. Bus grant request time.
• Transfer the entire block of data at transfer rate of device because the device is usually slow than the speed at which the data can be transferred to CPU.
• Release the control of the bus back to CPU So,

Total time taken to transfer the N bytes = Bus grant request time + (N) * (memory transfer rate) + Bus release control time.

• Buffer the byte into the buffer & Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)
• Transfer the byte (at system bus speed) & Release the control of the bus back to CPU.

I/O interface intro

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