Luyang Li

- Designed a LDO with Bandgap reference, Error amplifier, Thermal shutdown, Enable and Output driver blocks under TSMC 0.25um process technology
- Implemented the bandgap reference by constant Gm biasing circuit structure and achieved 1.225V internal reference(w/ maximum 0.01V variation among -40 °C to 110 °C and different corners in post-layout simulation)
- Executed transistor sizing, stability analysis and compensation, physical layout using VLSI symmetry technique and post layout… Show more

- Designed a LDO with Bandgap reference, Error amplifier, Thermal shutdown, Enable and Output driver blocks under TSMC 0.25um process technology
- Implemented the bandgap reference by constant Gm biasing circuit structure and achieved 1.225V internal reference(w/ maximum 0.01V variation among -40 °C to 110 °C and different corners in post-layout simulation)
- Executed transistor sizing, stability analysis and compensation, physical layout using VLSI symmetry technique and post layout verification across different PVT corners
- Achieved the following requirements:
• Max current 1.5A w/ heavy load
• High PSRR >49dB at 10KHz
• Ultra low noise(24 uVRMS)
• Very low dropout voltage(180 mV at full load)
• Thermal shutdown(turn off when temperature goes beyond 165 °C) Show less

-Designed a VLSI Bandgap circuit in TSMC 0.25um CMOS technology with symmetry methodologies by Beta-multiplier reference
-Implemented the output bandgap voltage of 1.2V (+/-10mV) and verified the design on different process corners with the temperature from -40 °C to 110 °C
-Achieved at least 63 dB in gain, 45 dB in PSRR and 56 degree in phase margin on different process corners

-Designed a module capable of performing 32 bit multiplication using booth encoding and different kinds of compressors by Verilog
-Constructed the testbench to verify the functionality of the Verilog code in behavioral level, Register transfer level(RTL) and Post-layout level by ModelSim
-Synthesized the design using Cadence RTL compiler and performed Automatic place and route (APR) using Cadence6 encounter by using the .LEF and .LIB files obtained from the designed standard cell library

- Designed a PLL with input 100MHZ and output 1.6GHZ frequency with Phase frequency detector (PFD), Charge bump, Loop filter, Ring based symmetric VCO and 1/16 Divider by TSMC 0.18um process technology
- Selected bandwidth of around 6.67MHz with a Q-factor of 0.7 in order to avoid ringing effect at high frequencies
- Constructed a ring based symmetric VCO that provides a highly stable four-phase clock outputs with the frequency range from 1GHZ to 3.5GHZ
- Implemented the VLSI Phase… Show more

- Designed a PLL with input 100MHZ and output 1.6GHZ frequency with Phase frequency detector (PFD), Charge bump, Loop filter, Ring based symmetric VCO and 1/16 Divider by TSMC 0.18um process technology
- Selected bandwidth of around 6.67MHz with a Q-factor of 0.7 in order to avoid ringing effect at high frequencies
- Constructed a ring based symmetric VCO that provides a highly stable four-phase clock outputs with the frequency range from 1GHZ to 3.5GHZ
- Implemented the VLSI Phase frequency detector (PFD) circuit based on digital logic gates and the 1/16 divider by using True Single Phase Clock(TSPC) Flip-flop
- Obtained the total estimated layout area of the PLL approximitely equals 72700 um sq.
- Achieved 470.52uW in power dissipation on the transient current Show less

-Designed an Operational Transconductance Amplifier(OTA) with 55.28dB in Gain and 168.6MHZ in Gain-Bandwidth Product by Cadence5
-Enhanced Output Impedance OTA with a Common Source Buffer
-Implemented a layout with Layout-Versus-Schematic (LVS) and Design-Rule-Check (DRC) clean

- Designed a folded-cascode operational amplifier with class AB output buffer and a very high gain(over 100dB) by Cadence5
- Achieved 90.66 degree in Phase margin and 31.41dB in Gain margin
- Obtained a 94.02dB in PSRR+ and 84.52dB in PSRR- and a very high CMRR:149.2dB in 10KHZ
- Implemented a relative low supply voltage:3V and low quiescent power consumption: 1.05mW

-Designed a 16 entry, 16 bit wide dynamic register file of schematic, layout and Hspice simulation by using SAED 32nm PDK technology
-Constructed the “one hot” decoded addresses for both write and read word line
-Implemented the design with Cadence Virtuoso and obtained the layout area of 591um^2 and EDP of 254.8 (ps*pJ) respectively

-Implemented Monte Carlo method to simulate an extended (8,4) Hamming code and used this code with binary antipodal signaling over AWGN
-Plotted the probability of error(Pm) versus signal noise ratio (Eb/N0) by using hard decision decoding(HDD) and soft decision decoding(SDD) respectively

-Implemented Frequency Domain Adaptive Filter(FDAF) to eliminate the noise and generated a clean speech by LMS algorithm and FFT
-Plotted error convergence curves by different FFT size and acquired best SNR and coefficient of ANC under random noisy signal and music background
-Plotted three-dimensional figure of filter coefficients vs iteration and frequency in dB by mesh function in MATLAB