Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK. TT-Ascalon is Tenstorrent’s high-performance RISC-V CPU, built on open standards to provide maximum flexibility and architectural control. It is based on the open RISC-V ISA and is RVA23 compliant. A central focus of the Ashling–Tenstorrent collaboration is comprehensive trace support, built on the RISC-V standard N-Trace architecture. RiscFree integrates with Tenstorrent’s Ascalon CPUs to capture detailed trace data across multi-core systems, enabling real-time visibility into instruction execution, memory transactions, and key system events. In addition to N-Trace, Tenstorrent’s Debug Signal Trace (DST) infrastructure has been fully implemented in its Ascalon CPUs, providing access to critical micro-architectural signals alongside standard trace data during post-silicon validation. DST enhances debugging, performance analysis, and coverage, and is fully supported by Ashling’s RiscFree tools—enabling deep trace visibility with minimal integration overhead. Learn more here: https://lnkd.in/gthF_9uj #RISCVEverwhere #DEBUG #Tenstorrent
𝗘-𝗧𝗿𝗮𝗰𝗲 (“Efficient Trace”) and 𝗡-𝗧𝗿𝗮𝗰𝗲 (“Nexus based IEEE-5001”) are both ratified RISC V trace standards for encoding: • RISC-V E-Trace (Efficient Trace) Specification https://drive.google.com/file/d/1iijHsZB7YXW0A2HuuzHo5QTZSKrO_KbW/view?usp=drive_link • RISC-V N-Trace (Nexus-based Trace) Specification https://github.com/riscv-non-isa/tg-nexus-trace/blob/main/ratified/1.0/RISC-V-N-Trace.pdf Both use the same common control and physical connectorising interfaces so config etc is unified regardless of encoding used: • RISC-V 𝗧𝗿𝗮𝗰𝗲 𝗖𝗼𝗻𝘁𝗿𝗼𝗹 Specification https://github.com/riscv-non-isa/tg-nexus-trace/blob/main/ratified/1.0/RISC-V-Trace-Control-Interface.pdf • RISC-V 𝗧𝗿𝗮𝗰𝗲 𝗖𝗼𝗻𝗻𝗲𝗰𝘁𝗼𝗿𝘀 Specification https://github.com/riscv-non-isa/tg-nexus-trace/blob/main/ratified/1.0/RISC-V-Trace-Connectors.pdf
Another great partnership!
How is N-Trace different from E-trace. Is there a diagram for the structure of N-Trace from the working group.
CEO at Ashling
1moThink of Trace as a 𝗳𝗹𝗶𝗴𝗵𝘁 𝗿𝗲𝗰𝗼𝗿𝗱𝗲𝗿 for your software/hardware which can record and show what actually happened without stopping or intruding on your embedded system. 𝗞𝗲𝘆 𝗥𝗜𝗦𝗖-𝗩 𝗧𝗿𝗮𝗰𝗲 𝗖𝗼𝗻𝗰𝗲𝗽𝘁𝘀: • 𝗣𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 𝗯𝗿𝗮𝗻𝗰𝗵 𝘁𝗿𝗮𝗰𝗲: A non-intrusive way to see program flow by reporting only PC changes (branches, jumps/calls/returns, interrupts/exceptions) from a known start point, while inferring all sequential instructions from the executed program binary. • 𝗘𝗻𝗰𝗼𝗱𝗶𝗻𝗴: On-chip logic compresses program execution information into compact trace packets—typically taken/not-taken outcomes and targets for un-inferable jumps/traps—so it can be streamed or stored with minimal bandwidth requirements. • 𝗗𝗲𝗰𝗼𝗱𝗶𝗻𝗴: Host software reconstructs exact execution by combining those captured packets with the program binary (typically an ELF file), replaying sequential instructions and applying the reported discontinuities, either live or offline.