Agenda

Introduction: SystemVerilog Motivation

Vassilios Gerousis, Infineon Technologies Accellera Technical Committee Chair

Session 3: SystemVerilog Assertions Language Tutorial

Bassam Tabbara, Novas Software

Technology and User Experience

Alon Flaisher, Intel

Session 1: SystemVerilog for Design Language Tutorial

Johny Srouji, Intel

Using SystemVerilog Assertions and Testbench Together

Jon Michelson, Verification Central

User Experience
Matt Maidment, Intel

Session 4: SystemVerilog APIs

Doug Warmke, Model Technology

Session 2: SystemVerilog for Verification Language Tutorial

Tom Fitzpatrick, Synopsys

Session 5: SystemVerilog Momentum Verilog2001 to SystemVerilog

Stuart Sutherland, Sutherland HDL

User Experience
Faisal Haque, Verification Central
Lunch: 12:15 1:00pm

SystemVerilog Industry Support

Vassilios Gerousis, Infineon
End: 5:00pm

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Testbench : Recurring Theme

Increase Level of Abstractions
Timing Synchronization Data type Data manipulation

Eliminate Static Limitations

Dynamic data Dynamic fan-out Dynamic processes
Testbench environments are much more like software programs than like hardware descriptions
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New Basic Data Types

String
Arbitrary length char array. Automatically resized.

Arrays
Dynamic and associative

Mailbox and Semaphore

Built-in synchronization classes.

Event Variables
Can be used in assignments and as arguments

Class
Allows object-oriented programming
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Dynamic Arrays
Declaration syntax
<type> <identifier> [ ]; bit[3:0] dyn[ ];

dyn

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Dynamic Arrays
Declaration syntax
<type> <identifier> [ ]; bit[3:0] dyn[ ];
bit[3:0] fix[0:3];

Initialization syntax
<array> = new[<size>]; dyn = new[4];

dyn
A B C D

A B C D

Size method
function int size(); int j = dyn.size;//j=4

Resize syntax
<array> = new[<size>](<src_array>); dyn = new[j * 2](fix);

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Dynamic Arrays
Declaration syntax
<type> <identifier> [ ]; bit[3:0] dyn[ ];

Initialization syntax
<array> = new[<size>]; dyn = new[4];

dyn
A B C D

Size method
function int size(); int j = dyn.size;//j=4

Resize syntax
<array> = new[<size>](<src_array>); dyn = new[j * 2](fix);

Delete method
function void delete(); dyn.delete; // dyn is now empty
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Associative Arrays
Sparse Storage Elements Not Allocated Until Used Index Can Be of Any Packed Type, String or Class Declaration syntax
<type> <identifier> [<index_type>]; <type> <identifier> [*]; // arbitrary type

Example
struct packed {int a; logic[7:0] b} mystruct; int myArr [mystruct]; //Assoc array indexed by mystruct

Built-in Methods
num(), delete([index]), exists(index); first/last/prev/next(ref index); Ideal for Dealing with Sparse Data
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Processes and Threads

program

a b c a b c a b c a b c

fork a;b;c; join fork a;b;c; join_any fork a;b;c; join_none

Threads created via forkjoin Threads execute until a blocking statement

wait for: (event, mailbox, semaphore, variable, etc.)

$exit terminates the main program thread

Multiple Independent Threads

fork a;b;c; Maximize Stimulus Interactions join_any disable fork;// kill all child processes fork a;b;c; join_any wait fork;// wait for children to complete #10; $exit
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Inter-Process Synchronization
Events enhanced from V2K
Events are variables can be copied, passed to tasks, etc. event.triggered; // persists throughout timeslice, avoids races wait_order(), wait_any(), wait_all(<events>);

Semaphore Built-in Class

Synchronization for arbitration of shared resources, keys. Mutual Exclusivity control KEYS Built-in methods: get, put, try_get

// main program .. semaphore shrdBus =new; ... task go_cpu(id, ref event ev) begin ... @(ev) shrdBus.get () ...//access granted ...//activity on the cpu bus shrdBus.put() Cache ... endtask

shared bus
semaphores

CPU1

CPU2

Cache

// usage, forking parallel // threads for cpu access event ev1,ev2; ... fork go_cpu(cpu1,ev1); go_cpu(cpu2,ev2); ... join ...

Guarantees Race-Free Synchronization Between Processes

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Mailbox: communication
Mailbox features
FIFO message queue: passes data between threads Can suspend thread, used for data checking

Mailbox built-in methods

new(), num(), put(), try_put(), get(), try_get(), peek(), try_peek()
Testbench compares the actual output with expected output [Packets] mailbox pktMbx = new; pktMbx.put(inPkt1); pktMbx.get(outPkt); compare_twoPackets;
Packet 2 Packet 1 Packet 3

Packet Stimulus

Packet 4

Compare DUT Input to Design

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output

Skews and Sampling: Why?

clock

Examine current state Compute next move

Bet more money

Need the steady state !

Shoot
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Skew Declaration
Specify Synchronous Sample / Drive Times
sample here
clock

drive here Input skew is for sampling Output skew is for driving

skew

input

Default input skew is 1step Default output skew is 0.

skew

output

clock edge (event)

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Synchronous Interfaces: Clocking

device
bus clk enable full data[7:0] empty

Synchronous Interface

clocking bus @(posedge clk); default input #1ns output #2ns; input inout output output #6ns endclocking enable, full; data; empty; reset = top.u1.reset;

Clocking Event clock Default I/O skew Hierarchical signal Testbench Uses: bus.enable bus.data ...

Override Output skew

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Default Clocking and Synchronous Drives

Designate one clocking as default
default clocking modA.clkDomain;

One default per module, interface, program Cycle Delay Syntax:

## <integer_expression> ##5; // wait 5 cycles ##1 bus.data <= 8hz;// wait 1 (bus) cycle and then drive data ##2; bus.data <= 2;// wait 2 default clocking cycles, then drive data bus.data <= ##2 r;// remember the value of r and then drive data 2 (bus) cycles later
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SystemVerilog Enhanced Scheduling

Previous Time Slot

Active

Inactive

NBA

Read-Only

Next Time Slot

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SystemVerilog Enhanced Scheduling

Previous Time Slot

Preponed

Active Verilog 2001

Inactive
Sample Stable Values

NBA
Evaluate Assertions

Observe SystemVerilog 3.1 Reactive Postponed

Execute TestBench
Next Time Slot

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Enhanced Scheduling in SystemVerilog

Avoids Race Conditions Between Testbench and Design Guarantees that Assertions and Testbench have Access to Stable Values Allows Testbench to React to Assertions (Pass or Fail) Ensures Common Semantics between Simulation, Formal Verification, Synthesis, HW Accelerators, Emulation, etc.
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Program Block
Purpose: Identifies verification code A program differs from a module
Only initial blocks allowed Special semantics
Executes in Reactive region design clocking/assertions program program name (<port_list>); <declarations>;// type, func, class, clocking <continuous_assign> initial <statement_block> endprogram
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Object-Oriented Programming
Organize programs in the same way that objects are organized in the real world Break program into blocks that work together to accomplish a task, each block has a well defined interface Focuses on the data and what you are trying to do with it rather than on procedural algorithms
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Class A blueprint for a house

Program element containing related group of features and functionality. Encapsulates functionality Provides a template for building objects

Object The actual house

An object is an instance of a class

Properties It has light switches

Variables specific to the class

Methods Turn on/off the lights

Tasks/functions specific to the class

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Class Basics
Class Definitions Contain Data and Methods Classes Are Instantiated Dynamically to Create Objects
Static members create a single element shared by all objects of a particular class type

Objects Are Accessed Via Handles

Safe Pointers, Like Java

Classes Can Inherit Properties and Methods From Other Classes Classes Can Be Parameterized
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Class Definition
Definition syntax
class name; <data_declarations>; <task/func_decls>; endclass
extern keyword allows for out-of-body method declaration class Packet; bit[3:0] cmd; int status; myStruct header; function int get_status(); return(status); endfunction extern task set_cmd(input bit[3:0] a); endclass

:: operator links method declaration to Class definition

task Packet::set_cmd(input bit[3:0] a); cmd = a; endtask

Note: Class declaration does not allocate any storage

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Class Instantiation
Objects Allocated and Initialized Via Call to the new Constructor Method
All objects have built-in new method
No args Allocates storage for all data properties
Packet myPkt = new;

myPkt
class Packet; ... function new(); cmd = IDLE; endfunction endclass Packet myPkt = new;
cmd status header
START IDLE 5

User-defined new method can initialize and/or do other things

class Packet; ... function new(input int a); cmd = START; status = a; endfunction endclass Packet myPkt = new(5); // myPkt.status = 5

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Class Inheritance & Extension

Keyword extends Denotes Hierarchy of Definitions
Subclass inherits properties and methods from parent Subclass can redefine methods explicitly Packet:
cmd status header
set_cmd cmd = a; get_status

class ErrPkt extends Packet; bit[3:0] err; function bit[3:0] show_err(); return(err); endfunction task set_cmd(input bit[3:0] a); cmd = a+1; endtask // overrides Packet::set_cmd endclass

ErrPkt:
cmd status header err
get_status show_err set_cmd cmd = a+1;

Allows Customization Without Breaking or Rewriting Known-Good Functionality in the Base Class
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Class Hierarchy
Class members can be hidden from external access
local members can only be referenced from within the class, not from a subclass protected members can be referenced from within a subclass
class Base; local int i; int a,d; protected task set_i(input int i); this.i = i; endtask function new();...endfunction endclass class Sub extends Base; int a; function new(); super.new();... endfunction task set_a(input int c); a = c; super.a = c+1; set_i(c); // inherited method endtask endclass

this pointer refers to current instance super pointer refers to parent class

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Class Hierarchy
Class members can be hidden from external access
local members can only be referenced from within the class protected members can be referenced from within a subclass
class Base; local int i; int a,d; protected task set_i(input int i); this.i = i; endtask function new();...endfunction endclass class Sub extends Base; int a; function new(); super.new();... endfunction task set_a(input int c); a = c; super.a = c+1; set_i(c);// inherited endtask endclass

this pointer refers to current instance super pointer refers to parent class

Sub S = new; initial begin S.i = 4; // illegal i is local to Base S.set_i(4);// illegal set_i is protected S.a = 5; // legal Base::a is hidden by Sub::a S.set_a(5);// legal set_a is unprotected S.d = 3;// legal d is inherited from Base end 117 DAC2003 Accellera SystemVerilog Workshop

Parameterized Classes
Allows Generic Class to be Instantiated as Objects of Different Types
Uses modulelike parameter passing
class vector #(parameter int size = 1;); bit [size-1:0] a; endclass vector #(10) vten; // object with vector of size 10 vector #(.size(2)) vtwo; // object with vector of size 2 typedef vector#(4) Vfour; // Class with vector of size 4 class stack #(parameter type T = int;); local T items[]; task push( T a ); ... endtask task pop( ref T a ); ... endtask endclass stack i_s; // default: a stack of ints stack#(bit[1:10]) bs; // a stack of 10-bit vector stack#(real) rs; // a stack of real numbers stack#(Vfour) vs; // stack of classes

Avoid Writing Similar Code More than Once

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Working With Objects

After calling new( ), values can be assigned to the object variables Each object created from the class has a different name and a separate memory space Data and subroutines are accessed through the object handle (like a pointer) Object Destruction/De-allocation
De-allocation of memory is taken care of automatically ( like Java, unlike C++)
When an object is no longer being referenced, the memory used by this object is released No destructors No memory leaks or unexpected side effects
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Constrained Random Simulation

Test Scenarios Constraints Constraints Valid Inputs Specified as Constraints Declarative

Input Space
Design

Constraint Solver Find solutions

Valid

Exercise Hard-to-Find Corner Cases While Guaranteeing Valid Stimulus

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Random Constraints
Constraints are built onto the Class system Random variables use special modifier:
rand random variable randc random cyclic variable

Object is randomized by calling randomize( ) method

Automatically available for classes with random variables.

User-definable methods
pre_randomize() post_randomize()

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Basic Constraints
Constraints are Declarative
class Bus; rand bit[15:0] addr; rand bit[31:0] data; constraint word_align {addr[1:0] == 2b0;} endclass

Calling randomize selects values for all random variables in an object such that all constraints are satisfied
Generate 50 random data and word_aligned addr values
Bus bus = new; repeat (50) if ( bus.randomize() == 1 ) // 1=success,0=failure $display ("addr = %16h data = %h\n", bus.addr, bus.data); else $display ("Randomization failed.\n");
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Layered Constraints
Constraints Inherited via Class Extension
Just like data and methods, constraints can be inherited or overridden
typedef enum { low, high, other } AddrType ;

type variable selects class MyBus extends Bus; rand AddrType type; address range constraint addr_rang { ( type == low ) => addr in { [ 0 : 15] }; ( type == high ) => addr in { [128 : 255] }; } endclass

Bus::word_align Constraint is also active

Inheritance allows layered constraints Constraints can be enabled/disabled via constraint_mode() method
Allows Reusable Objects to be Extended and/or Constrained to Perform Specific Functions
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In-Line Constraints
Additional Constraints In-line Via
obj.randomize()with <constraint_blk>
task exerBus(MyBus m); int r; r = m.randomize() with {type==small}; endtask
Force type to be small

In-Line Constraints Pick Up Variables From the Object

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SystemVerilog Testbench Language Summary

Testbench Extensions Verification Extenstions Useful for modeling
environment
Classes Random Constraints Pass-by-Reference Process Control
Interprocess communication Synchronization

Enhanced Scheduling Program Block Clocking Domains Assertions

Extended data types

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Testbench Language Evolution

Advantages of Extending an Existing Language
SystemVerilog: Builds on Verilog Easy to Use/Debug All the Power in One Tool
Productivity

Separate Verification Language: Have to Start Over From Scratch Separate tool = Bottleneck Different Language from Design

Basic Verification Using Verilog

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