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* The document contains the schematic netlist for different electronic circuits including CMOS NOT gate, CMOS NAND gate, CMOS NOR gate, Astable Multivibrator, Monostable Multivibrator, Bistable Multivibrator, Butterworth 2nd order LPF, A/D converter, D/A converter, and Differential Amplifier. * The netlist describes the components used and their connections in each circuit through lines beginning with identifiers like M_M, U_DSTM, Q_Q, R_R, C_C, V_V etc. * Times, voltages, and other parameters are provided for components like stimulators and switches.

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Henri Dass
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72 views9 pages

Ps Ice Docs

* The document contains the schematic netlist for different electronic circuits including CMOS NOT gate, CMOS NAND gate, CMOS NOR gate, Astable Multivibrator, Monostable Multivibrator, Bistable Multivibrator, Butterworth 2nd order LPF, A/D converter, D/A converter, and Differential Amplifier. * The netlist describes the components used and their connections in each circuit through lines beginning with identifiers like M_M, U_DSTM, Q_Q, R_R, C_C, V_V etc. * Times, voltages, and other parameters are provided for components like stimulators and switches.

Uploaded by

Henri Dass
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CMOS NOT GATE:

* Schematics Netlist *
U_DSTM3
STIM(1,1)
+ $G_DPWR $G_DGND
+ $N_0001
+ IO_STM
+ IO_LEVEL=0
+ 0s 0
+ 20m 1
+ 30m 0
M_M2
$N_0003 $N_0001 $N_0002 $N_0002
MbreakP
+ L=10u
+ W=100u
M_M1
$N_0003 $N_0001 0 0 MbreakN
+ L=10u
+ W=100u
V_V1
$N_0002 0 5V

Output

CMOS NAND Gate:

* Schematics Netlist *
M_M6
$N_0002 $N_0001 0 0 MbreakN
M_M7
$N_0005 $N_0003 $N_0004 $N_0005 MbreakP
M_M5
$N_0004 $N_0003 $N_0002 0 MbreakN
M_M1
$N_0005 $N_0001 $N_0004 $N_0005 MbreakP
V_V1
$N_0005 0 5V
U_DSTM1
STIM(1,1)
+ $G_DPWR $G_DGND
+ $N_0003
+ IO_STM
+ IO_LEVEL=0
+ TIMESTEP=6
+ 0ms 0
+ 5ms 1
+ 10ms 0
+ 15ms 1
+ 20ms 0
+ 25ms 1
U_DSTM2
STIM(1,1)
+ $G_DPWR $G_DGND
+ $N_0001
+ IO_STM
+ IO_LEVEL=0
+ TIMESTEP=6
+ 0ms 0
+ 5ms 1
+ 10ms 0
+ 15ms 1
+ 20ms 0
+ 25ms 1

OUTPUT:

CMOS NOR GATE:


* Schematics Netlist *
M_M3
$N_0002 $N_0001 0 0 MbreakN
M_M4
$N_0002 $N_0003 0 0 MbreakN
M_M2
$N_0004 $N_0001 $N_0002 $N_0005 MbreakP
M_M1
$N_0005 $N_0003 $N_0004 $N_0005 MbreakP
V_V1
$N_0005 0 5V
U_DSTM1
STIM(1,1)
+ $G_DPWR $G_DGND
+ $N_0003
+ IO_STM
+ IO_LEVEL=0
+ TIMESTEP=5
+ 0ms 0
+ 5ms 1
+ 10ms 0
+ 15ms 1
+ 20ms 0
U_DSTM2
STIM(1,1)
+ $G_DPWR $G_DGND
+ $N_0001
+ IO_STM
+ IO_LEVEL=0
+ TIMESTEP=5
+ 0ms 0
+ 5ms 1
+ 10ms 0
+ 15ms 1
+ 20ms 0

OUTPUT:

Astable Multivibrator:

* Schematics Netlist *
Q_Q1
Q_Q2
V_V1
R_R4
R_R3
R_R2
C_C2
R_R1
C_C1

OUTPUT:

$N_0002 $N_0001 0 Q2N3904


$N_0004 $N_0003 0 Q2N3904
$N_0005 0 9v
$N_0002 $N_0005 2.7k
$N_0003 $N_0005 150k
$N_0001 $N_0005 150k
$N_0002 $N_0003 10n
$N_0004 $N_0005 2.7k
$N_0001 $N_0004 10n IC=5V

Monostable Multivibrator:
* Schematics Netlist *

Q_Q1
$N_0002 $N_0001 0 Q2N3904
Q_Q2
$N_0004 $N_0003 0 Q2N3904
V_V2
$N_0005 0 9V
R_R3
$N_0002 $N_0005 4.7k
R_R4
$N_0003 $N_0005 180k
C_C2
$N_0002 $N_0003 10000p
V_V1
0 $N_0006 -9V
R_R1
$N_0006 $N_0001 66.66k
R_R2
$N_0001 $N_0004 10k
R_R5
$N_0004 $N_0005 4.7k
C_C1
$N_0001 $N_0004 1000p
D_D1
$N_0001 $N_0007 D1N4148
V_V3
$N_0007 0 DC 1v AC 4v
+PULSE 1v 3v 0ns 0ns 5us 20us

OUTPUT:

Bistable Multivibrator:

* Schematics Netlist *

Q_Q1
$N_0002 $N_0001 $N_0003 Q2N3904
Q_Q2
$N_0005 $N_0004 $N_0003 Q2N3904
V_V1
$N_0006 0 12V
R_R7
$N_0005 $N_0006 2.5k
R_R6
$N_0002 $N_0006 2.5k
R_R2
$N_0001 $N_0005 16k
R_R3
0 $N_0001 3.2k
R_R5
0 $N_0004 3.2k
C_C1
$N_0005 $N_0007 1u
R_R1
0 $N_0003 1.2k
D_D1
$N_0002 $N_0008 D1N4148
D_D2
$N_0005 $N_0008 D1N4148
R_R4
$N_0004 $N_0002 16k
V_V2
$N_0007 0 DC 1v AC 5v
+PULSE 1v 5v 0 0 0 5u 20u
D_D3
$N_0008 $N_0006 D1N4148

Output:

Butterworth 2nd order LPF:


* Schematics Netlist *

X_U1
$N_0001 $N_0002
$N_0003 $N_0004 $N_0005 LF411
R_R1
$N_0009 $N_0008 1.59k
R_R3
$N_0008 $N_0001 1.59k
R_R2
0 $N_0002 1k
R_R4
$N_0002 $N_0005 586
V_V1
$N_0003 0 15V
C_C2
$N_0008 $N_0005 0.1u
C_C1
$N_0001 0 0.1u
V_V3
$N_0009 0 DC 0V AC 1V
V_V2
0 $N_0004 15V

OUTPUT:

A/D converter:

* Schematics Netlist *

R_R2
$N_0001 0 1k
R_R3
$N_0002 0 1k
R_R4
$N_0004 $N_0003 1k
R_R5
0 $N_0004 1k
R_R6
$N_0003 $N_0005 1k
V_V1
$N_0005 0 9V
V_V2
$N_0006 0 3V
R_R1
$N_0007 0 1k
E_U1
$N_0007 0 VALUE
{LIMIT(V($N_0006,$N_0003)*1E6,15V,+15V)}
E_U2
$N_0001 0 VALUE
{LIMIT(V($N_0006,$N_0004)*1E6,15V,+15V)}
E_U3
$N_0002 0 VALUE
{LIMIT(V($N_0006,0)*1E6,-15V,+15V)}

OUTPUT:

D/A Converter:

OUTPUT:

* Schematics Netlist *

R_R6
$N_0001 0 1k
V_V1
$N_0002 0 1V
R_R5
$N_0003 $N_0001 10k
X_U1
$N_0004 $N_0002 Sw_tClose PARAMS:
tClose=30ms ttran=1u
+ Rclosed=0.01 Ropen=1Meg
X_U2
$N_0005 $N_0002 Sw_tClose PARAMS:
tClose=30ms ttran=1u
+ Rclosed=0.01 Ropen=1Meg
X_U3
$N_0006 $N_0002 Sw_tClose PARAMS:
tClose=30ms ttran=1u
+ Rclosed=0.01 Ropen=1Meg
X_U4
$N_0007 $N_0002 Sw_tClose PARAMS:
tClose=30ms ttran=1u
+ Rclosed=0.01 Ropen=1Meg
X_U5
0 $N_0003 -15v +15v $N_0001 uA741
R_R4
$N_0003 $N_0007 20k
R_R3
$N_0003 $N_0006 20k
R_R2
$N_0003 $N_0005 20k
R_R1
$N_0003 $N_0004 20k

Differential Amplifier:
* Schematics Netlist *

Q_Q1
Q2N3904
Q_Q2
Q2N3904
R_R1
R_R2
R_R5
V_V4
R_R4
R_R3
V_V5
V_V6
V_V1

OUTPUT:

$N_0002 $N_0001 $N_0003


$N_0005 $N_0004 $N_0003
$N_0002 $N_0006
$N_0005 $N_0006
$N_0003 $N_0007
0 $N_0007 12v
$N_0001 $N_0008
$N_0009 $N_0004
$N_0008 0 60mV
$N_0009 0 40mV
$N_0006 0 12V

4.5k
4.5k
5k
120
120

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