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Simulated Output: Wallace:tree MR (3..0) MD (3..0) Booth - Encoder:booth Partial:pp

1) The document contains the RTL (register transfer level) views for a multiplier circuit called mul_test1. 2) It shows the design contains a Booth encoder, partial product generator (PPG), and Wallace tree. 3) The Wallace tree uses a network of full adders (FAs) and half adders (HAs) to sum the partial products and produce the final product in result[7..0].

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senthilvl
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78 views5 pages

Simulated Output: Wallace:tree MR (3..0) MD (3..0) Booth - Encoder:booth Partial:pp

1) The document contains the RTL (register transfer level) views for a multiplier circuit called mul_test1. 2) It shows the design contains a Booth encoder, partial product generator (PPG), and Wallace tree. 3) The Wallace tree uses a network of full adders (FAs) and half adders (HAs) to sum the partial products and produce the final product in result[7..0].

Uploaded by

senthilvl
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Simulated output

Rtl view for mul_test1

booth_encoder:booth
mr[3..0]
md[3..0]

partial:pp

wallace:tree

mr[3..0]

x[3..0]

x[3..0]

r0[7..0]

r0[7..0]

md[3..0]

z[3..0]

z[3..0]

r1[7..0]

r1[7..0]

md[3..0]

r2[7..0]

r2[7..0]

mr[3..0]

r3[7..0]

r3[7..0]

Booth encoder rtl

result[7..0]

result[7..0]

z~2
md[3..0]
mr[3..0]
z~1

z[3..0]

z~0

x~2

x~1

x~0

x[3..0]

Ppg rtl

Add0
r1[7]$latch

A [3 ..0 ]

m r[3..0]
4' h1 --

B [3 ..0 ]

0
1

ADDER

always 0~4

r1[7]~0

x[3..0]
z[3..0]

PRE
D

ENA
CLR

r1[6]$latch
always 0~5

r1[7]~1

r2[7..0]

PRE
D

ENA
CLR
2' h0 --

always 0~3

r1[5]$latch
PRE
D

ENA
CLR

r1[4]$latch
PRE
D

r1[7..0]

ENA
CLR

r1[3]$latch
0
1

r1[3]

1' h0 --

PRE
D

ENA
CLR

r1[2]$latch
0
1

r1[2]

PRE
D

ENA
CLR

r1[1]$latch
0
1

always 0~1

r1[1]

PRE
D

ENA
CLR

r0[7]$latch
0
1

always 0~2

r0[7]~0
r0[7]~1

PRE
D

ENA
CLR

r0[6]$latch
PRE
D

ENA
CLR

always 0~0

r0[5]$latch
PRE
D

ENA
CLR

r0[4]$latch
PRE
D

ENA
CLR

r0[3]$latch
PRE
D

r0[7..0]

ENA
CLR

r0[2]$latch
0
1

r0[2]

PRE
D

ENA
CLR

r0[1]$latch
0
1

r0[1]

PRE
D

ENA
CLR

r0[0]$latch
0
1

always 0~10

r0[0]

PRE
D

ENA
CLR

r3[7]~0_OUT0

r3[7]~0
0

r3[5]_OUT0

r3[5]
0

r3[4]_OUT0

r3[4]
0

r3[3]_OUT0

always 0~7

r3[3]
0

r2[7]~0_OUT0

r2[7]~0
r2[4]$latch
0
1

always 0~8

r2[4]
r2[7]~1

PRE
D

ENA
CLR

r2[7]~1_OUT0
always 0~10_OUT0
r2[3]$latch

always 0~6
0
1

r2[3]

PRE
D

ENA
CLR

r2[2]$latch
0
1

r2[2]

PRE
D

ENA
CLR

always 0~11
always 0~11_OUT0
always 0~9
always 0~9_OUT0
r2[7]$latch_OUT0
r2[6]$latch_OUT0
r2[5]$latch_OUT0

always 0~6_OUT0

Wallace tree rtl


ha:ha10
r0[7..0]
r1[7..0]

sum

c_out

fa:fa11
c_in

c_out

c_in
x

ha:ha1

r2[7..0]

fa:fa12

sum

sum

c_out

fa:fa13

sum
c_out

c_in
x
y

fa:fa14

sum
c_out

c_in
x
y

fa:fa15

sum
c_out

c_in
x
y

fa:fa2
c_in

r3[7..0]

x
y

sum

sum

c_out

c_out

fa:fa7
c_in

x
y

sum

c_out

c_in

x
y

sum

c_out

c_in

x
y

sum

c_out

fa:fa17

sum
c_out

fa:fa18

c_in

sum
c_out

fa:fa9

fa:fa5
c_in

sum
c_out

fa:fa8

fa:fa4
c_in

c_in
sum

x
y

c_in
x

sum

ha:ha6

fa:fa3
c_in

fa:fa16

sum
c_out

sum

result[7..0]

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