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DFT DRC - PPT 0

The document discusses scan insertion for testing sequential elements on a chip. It explains that the tool first performs basic checks on the design before scan insertion. It then identifies all sequential elements for input/output controllability and observability. Any fault locations that cannot be controlled or observed from inputs/outputs may not be fully testable or testable at all. It also provides an overview of built-in self-test (BIST), which generates and analyzes test patterns internally to test circuits on a chip.

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Mohan Raj
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614 views3 pages

DFT DRC - PPT 0

The document discusses scan insertion for testing sequential elements on a chip. It explains that the tool first performs basic checks on the design before scan insertion. It then identifies all sequential elements for input/output controllability and observability. Any fault locations that cannot be controlled or observed from inputs/outputs may not be fully testable or testable at all. It also provides an overview of built-in self-test (BIST), which generates and analyzes test patterns internally to test circuits on a chip.

Uploaded by

Mohan Raj
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as ODP, PDF, TXT or read online on Scribd

Introduction

Prior to scan insertion, the tool performs limited rule


checks on the design

For scan insertion Tool identifies all sequential


elements I/O controlability and observability.

If tool fails to control or observe any fault location


from any PI's and PO's those locationstestable com
pletely or may not be testable

What Is BIST

On Chip/circuit

Test pattern generation

Response verification

Random pattern
generation,
very long tests
Response compression

Test Pattern Generation (TPG)

BIST
Control Unit

Circuitry Under Test


CUT

Test Response Analysis (TRA)

Introduction Introduction Prior to scan insertion, the tool performs limited rule checks on the design For scan insertio
What Is BIST What Is BIST On Chip/circuit • Test pattern generation • Response verification Random pattern generation,

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