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VHDL Code for Flip-Flops

The document contains VHDL code for 4 different types of flip-flops - SR, JK, D and T. The SR flip-flop code describes an entity with inputs S, R and outputs Q, QN. The JK flip-flop code describes an entity with inputs J, K, CLK and outputs Q, QN that changes states based on J and K values during rising clock edge. The D flip-flop code describes an entity with inputs D, CLK and output Q that takes the value of D during rising clock edge. The T flip-flop code describes an entity with inputs T, CLOCK and outputs Q, QN that toggles Q value depending on T during

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287 views4 pages

VHDL Code for Flip-Flops

The document contains VHDL code for 4 different types of flip-flops - SR, JK, D and T. The SR flip-flop code describes an entity with inputs S, R and outputs Q, QN. The JK flip-flop code describes an entity with inputs J, K, CLK and outputs Q, QN that changes states based on J and K values during rising clock edge. The D flip-flop code describes an entity with inputs D, CLK and output Q that takes the value of D during rising clock edge. The T flip-flop code describes an entity with inputs T, CLOCK and outputs Q, QN that toggles Q value depending on T during

Uploaded by

AdiHasan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

VHDL for SR Flip-flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRff is
Port ( S : in std_logic;
R : in std_logic;
Q : inout std_logic;
QN : inout std_logic);
end SRff;
architecture Behavior of SRff is
begin
process (S,R,Q,QN)
begin
Q <= R NOR QN;
QN <= S NOR Q;
end process;
end Behavior;

VHDL for JK Flip flop


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity JKff1 is
Port ( J : in std_logic;
K : in std_logic;
CLK : in std_logic;
Q : inout std_logic;
QN : inout std_logic);
end JKff1;
architecture Behaviorof JKff1 is
begin

process(CLK,J,K)
begin
if (CLK='1' and CLK'event)
then
if(J='0' and K='0') then
Q <=Q;
QN <=QN;
elsif(J='0' and K='1') then
Q <= 0';
QN <= '0';
elsif(J='1' and K='0') then
Q <= 1';
QN <= '1';
elsif(J='1' and K='1') then
Q <= NOT Q;
QN <= NOT QN;
end if;
end if;
end process;
end Behavior;

VHDL for D Flip-flop


LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY Dff IS
PORT ( D, Clk : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END Dff ;
ARCHITECTURE Behavior OF Dff IS
BEGIN
PROCESS ( Clk )
BEGIN
IF Clk EVENT AND Clk = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;

VHDL for T Flip flop


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Tff is
Port (
T : in std_logic;
CLOCK : in std_logic;
Q : inout std_logic;
QN : out std_logic);
END Tff;
ARCHITECTURE Behavior OF Tff IS
BEGIN
PROCESS(CLOCK)
BEGIN
IF (CLOCK = '0' and CLOCK'event) THEN
Q <= (T AND (NOT Q)) OR ((NOT T) AND Q);
END IF;
QN <= NOT Q;
END PROCESS;
END Behavior:

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