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Digital Electronics Test - Kollam

1. The document appears to be an exam for a Digital Electronics course, with two versions of the exam labeled Part A and Part B. 2. Part A consists of 5 multiple choice questions covering topics like combinational logic circuits, logic gates, parallel adders, K-map simplification, and flip flop implementations. 3. Part B consists of 3 long answer questions from a choice of 5, covering topics like BCD arithmetic, adder implementations, flip flop types, logic simplification techniques, and number systems.

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Santhanu Surendran
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134 views2 pages

Digital Electronics Test - Kollam

1. The document appears to be an exam for a Digital Electronics course, with two versions of the exam labeled Part A and Part B. 2. Part A consists of 5 multiple choice questions covering topics like combinational logic circuits, logic gates, parallel adders, K-map simplification, and flip flop implementations. 3. Part B consists of 3 long answer questions from a choice of 5, covering topics like BCD arithmetic, adder implementations, flip flop types, logic simplification techniques, and number systems.

Uploaded by

Santhanu Surendran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

YOUNUS INSTITUTE OF TECHNOLOGY

KANNANALLOOR P.O KOLLAM

Name...................................

DEPARTMENT OF ELECTRONICS AND COMMUNICATION


First Series Test September 2013
08.306 DIGITAL ELECTRONICS
Time: 2 Hours

Max. Marks: 50

Question code: A

Part A
Answer all questions.
1. Enlist the features of combinational logic circuits?
2. Draw the logic symbols, output expression and truth tables of the following gates
a) NAND b) NOR c) EXOR d) OR
3. What is a parallel adder and why it is known as a Ripple Carry adder?
4. Simplify the following expressions using a 4 variable KMAP
a) F(ABCD)=m(2,3,6,7,8,10,11,13,14) b) F(ABCD)=m(2,4,6,8,10,12,15)
5. Obtain the logic implementation and truth table of a JK flip flop and a D flip flop.

(5 x 4 = 20 Marks)

Part B
Answer any three
6. Solve the following function F(ABCD)=m(0,1,6,7,8,9,13,14,15) using Quine McClusky method and
draw its logic implementation
7. Design a full adder, write the expressions for sum and carry and implement it in AOI logic as well as
NAND
logic.
8. Implement the following functions using an 8:1 MUX
a. F(ABCD)= m(0,1,3,4,8,9,15)
b. F(ABCD)= m(0,1,2,4,6,9,12,14)
9. Explain VHDL and write the VHDL programs for half adder and full adder.
10. Describe shift registers in detail. Draw the logic implementations of SISO, SIPO, PIPO, PISO using
flipflops

(3 x 10 = 30 Marks)

YOUNUS INSTITUTE OF TECHNOLOGY


KANNANALLOOR P.O, KOLLAM

Name...................................

DEPARTMENT OF ELECTRONICS AND COMMUNICATION


First Series Test September 2013
08.306 DIGITAL ELECTRONICS
Time: 2 Hours

Max. Marks: 50

Question code: B

1.
2.
3.
4.
5.

Part A
Answer all questions.
Write a short note on Binary Codes and explain BCD arithmetic.
What is a Half Adder? Implement a half adder using AOI logic and NAND logic
What is meant by race around problem in JK Flip Flops?
Draw the circuit of a BCD Adder.
Obtain the logic implementation and truth table of an SR flip flop and a T flip flop
`

(5 x 4 = 20 Marks)
Part B
Answer any three

1.

Realize the following SOP expressions using K Map simplification


(a) F(ABCD)= m(0,1,2,3,4,6,8,9,10,11)
(b) F(ABC)= m(1,3,4,5,6,7)
(c) F(ABCD)= m(0,1,2,4,6,9,12,14)
2. Simplify the function S=m(1,2,4,5,6,8,9,12)+d(3,10,13,15) using Quine MuClusky method and implement
it using logic gates.
3. State and prove De Morgans theorem and simplify the following expressions using De Morgans theorem
(a) (A+BC)(AB+ABC)
(b) AB+A+AB
4. Explain VHDL and write the VHDL programs for half adder and full adder.
5. Write in Detail
(a) Binary number system
(b) Hexadecimal number system
(c) Octal number system
(d) Decimal Number system

(3 x 10 = 30 Marks)

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