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PRBS Generator Using VHDL Final

This document describes the design and implementation of a pseudo-random bit sequence (PRBS) generator using a linear feedback shift register (LFSR) in VHDL. It explains that an LFSR generates nearly random data through maximal length sequences. It then provides details on the structure of an LFSR, how PRBS works, and shows a flowchart and schematic for a 16-bit PRBS generator that taps the 15th, 4th, 2nd and 1st D-flip flops and feeds them back to the 1st DFF using XOR gates. Applications and advantages of using this approach are also listed.

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Alpesh Thesiya
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703 views17 pages

PRBS Generator Using VHDL Final

This document describes the design and implementation of a pseudo-random bit sequence (PRBS) generator using a linear feedback shift register (LFSR) in VHDL. It explains that an LFSR generates nearly random data through maximal length sequences. It then provides details on the structure of an LFSR, how PRBS works, and shows a flowchart and schematic for a 16-bit PRBS generator that taps the 15th, 4th, 2nd and 1st D-flip flops and feeds them back to the 1st DFF using XOR gates. Applications and advantages of using this approach are also listed.

Uploaded by

Alpesh Thesiya
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Design and Implementation

PRBS Generator Using VHDL

Prepared By, Guided By,


Divyesh Patel Prof. B. M. Chaudhari
Alpesh Thesiya
Tejas Shah
PROPERTIES

 The maximal length LFSR (Linear feedback


shift registers)
 generates data that is almost random.
 Maximal length (2^n) -1.
 000..00 – A special case.
 The problem: Choose the place for the XOR
which provides the maximal length.
Pseudo Random Bit Sequence
(PRBS)
 A Pseudorandom bit generator (PRBS) is
used to generate a random sequence of 1’s
and 0’s
 It is a good approach to use a PRBS
sequence as a testing driver than a regular
pulse wave sequence
How to construct a PRBS

D Q D Q D Q D Q D Q D Q
Data Data
IN OUT
CLK CLK CLK CLK CLK CLK

Clock
LFSR
 A linear feedback shift register (LFSR) is a shift
register whose input bit is a linear function of its
previous state. The only linear functions of single bits
are xor and inverse-xor; thus it is a shift register
whose input bit is driven by the exclusive-or (xor) of
some bits of the overall shift register value.
 Types Of LFSR:

Galois Type Fibonacci Type


Flowchart
Start
Shift Left with carry

Clear Register

Set the Left shift Count Bit Shift Right with carry
(N)

Tapping the Register Output


RET
Set the initial counter to ‘0’

Increment
No
Shift Right Register a bit

Count =N ?
Description

 16 DFF connect in series, the output of the 15th ,4th


, 2nd and 1 DFF will connect to a XOR logic gate
and feedback to the 1st DFF
DFF Symbol

D Q

CLK
DFF Schematic
16bit PSRB
16bit PSRB schematic
Simulation
Application
 Data Encryption/Decryption
 Digital Signal Processing
 Wireless Communications
 Built-in Self Test (BIST)
 Data Integrity Checksums
 Data Compression
 Direct Sequence Spread Spectrum
Advantages
 Variable Length LFSR
 Variable Tapping Mechanism
 Vary PN Sequence
Conclusion

As the PRBS generator using LFSR is easy


because of ease of construction from simple
electronics circuit, long periods, and very uniformly
distributed output. An LFSR is a linear system,
leading to fairly easy cryptanalysis.

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