Load eoable A select B select
A","
Write
Ddata n ",'vv
Coostant lo
o
MB select
BusA
Address Out
Data Out
A
Data lo
o FIGURE 7-9
Block Diagram of a Datapath
\
7-6 / Datapaths o 359
1
accesses occur in the same clock cycle.A Write input corresponding to the Load
Enable signal is algo provided. When at O,the Write signal prevents the registers
frombeing changed during that clock cycle. The size of the register file is 2m x n ,
wherem is the number of registe r address bits and n is the number of bits per regis-
ter.For the datapath in Figure 7-9, m = 2, giving four registers, and n is unspecified.
Since both the ALU and the shifter are shared processing units with outputs
that are selected by MUX F, it is convenient to group the two units and the MUX
together to form a shared function unit. Gray shading in Figure 7-9 highlights the
functionunit, which can be represented by the symbol given in Figure 7-18. The
inputsto the function unit are from Bus A and Bus B, and the output of the func-
Constant in
n
MB select
BusA n
Address out
Bus B n
Data out
FS'
V
C
N
Z
n
Data in
o FIGURE7-18
Block Diagram of Datapath Using lhe Register File and Function Unit
7-9 I Datapath Representation O 369
n ~-'r-' ~~ .u~ LU""-
Constant in
n
/1 ..I.
1 O
MB select MUXB
BusA T --,.
BusB
n
n
Address out
Data out
5
FS
V
C
N
Z
n
Data in
MD select
o FIGURE7-18
nL_'-~'