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PCI Peripheral Component Interface: Prof. Dr. Antônio Augusto Fröhlich

PCI (Peripheral Component Interface) is a standard for connecting hardware devices within a computer. It replaced the ISA (Industry Standard Architecture) bus. PCI supports 32-bit or 64-bit widths and synchronous data transfer speeds up to 132 MB/s for 32-bit PCI or 528 MB/s for 64-bit PCI. It allows for multiple bus masters, cache support, and parity error reporting. Transactions on the PCI bus involve an initiator that owns the bus and a target that is the recipient of read or write data transfers.

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0% found this document useful (0 votes)
76 views12 pages

PCI Peripheral Component Interface: Prof. Dr. Antônio Augusto Fröhlich

PCI (Peripheral Component Interface) is a standard for connecting hardware devices within a computer. It replaced the ISA (Industry Standard Architecture) bus. PCI supports 32-bit or 64-bit widths and synchronous data transfer speeds up to 132 MB/s for 32-bit PCI or 528 MB/s for 64-bit PCI. It allows for multiple bus masters, cache support, and parity error reporting. Transactions on the PCI bus involve an initiator that owns the bus and a target that is the recipient of read or write data transfers.

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Software/Hardware Integration

PCI
Peripheral Component Interface

LISHA/UFSC

Prof. Dr. Antônio Augusto Fröhlich


[email protected]
http://www.lisha.ufsc.br/~guto

March 2002
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The Standard
Software/Hardware Integration

More than a bus




PCI specifies the interaction between several




hardware components (mechanical, electrical,


timing, protocols)
Replacement for ISA


Used on IA-32, IA-64, Alpha, PowerPC,




Sparc64, and others

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Features
Software/Hardware Integration

32 or 64 bits (also 64 data and 32 address)




Synchronous operation


33 MHz ~ 132 MB/s


66 MHz ~ 528 MB/s


Down to 0 MHz

Single or multiple bus masters




Bus parity error reporting




Cache support


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Architectural Overview
Software/Hardware Integration

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Transactions
Software/Hardware Integration

Initiator (or Master)




Owns the bus and initiates the data transfer


Must also be a Target


Target (or Slave)




Target of the data transfer (read or write)


Agent


Any initiator or target on the bus


Burst transaction


More than one data phase


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Software/Hardware Integration

 


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Transactions

 



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Bus Signals
Software/Hardware Integration

CLK


Can be lowered to 0 MHz


IDSEL


Individual device select for configuration (one per


agent)
Allows address configuration

Arbitration (REQ/GNT)


Individual connections to/from arbiter


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Address Spaces
Software/Hardware Integration

Configuration space (256 bytes)


ž

Basic information about devices


Ÿ

Supports Plug-N-Play
Ÿ

Accessed by OS to perform settings


Ÿ

I/O space
ž

IBM PC (IA-32)
Ÿ

4 B to 2 GB per device
Ÿ

Memory space
ž

Everything else
Ÿ

16 B to 2 GB per device (> 4 K suggested)


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PCI Commands
Software/Hardware Integration

C/BE Command
0000 Interrupt acknowledge
0001 Special cycle Space
0010 I/O read I/O
0011 I/O write Memory
0110 Memory read Config
0111 Memory write
IDSEL 1010 Configuration read
IDSEL 1011 Configuration write
1100 Memory read multiple
1101 Dual address cycle
1110 Memory read line
1111 Memory write and invalidate

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Configuration Space Header
Software/Hardware Integration

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PCI Variations
Software/Hardware Integration

AGP
ž

Point-to-point protocol
 

Graphics on PCs
 

CardBus
ž

PCI in a PCMCIA form factor


 

Portable systems
 

CompactPCI
ž

PCI in a EUROCARD form factor


 

Passive backplane
 

Used in telecom and industrial applications


 

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