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Parking Lot Counter

The document describes using two pairs of photo sensors to monitor vehicle entry and exit from a parking lot with a single gate. The sensors output signals that can be used to determine if a vehicle is entering or exiting based on the sensors becoming blocked or unblocked in a specific sequence. An FSM and occupancy counter with Verilog code need to be designed that use the sensor signals to control the counter and indicate entry and exit events.

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2K views

Parking Lot Counter

The document describes using two pairs of photo sensors to monitor vehicle entry and exit from a parking lot with a single gate. The sensors output signals that can be used to determine if a vehicle is entering or exiting based on the sensors becoming blocked or unblocked in a specific sequence. An FSM and occupancy counter with Verilog code need to be designed that use the sensor signals to control the counter and indicate entry and exit events.

Uploaded by

saket512
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Consider a parking lot with a single entry and exit gate.

Two pairs of photo sensors are used


to monitor the activity of cars, as shown in figure below. When an object is between the
photo transmitter and the photo receiver, the light is blocked and the corresponding output is
asserted to 1. By monitoring the events of two sensors, we can determine whether a car is
entering or exiting or a pedestrian is passing through. For example, the following sequence
indicates that a car enters the lot:

Initially, both sensors are unblocked (i.e., the a and b signals are "00").
Sensor a is blocked (i.e., the a and b signals are " 10").
Both sensors are blocked (i.e., the a and b signals are "11 ").
Sensor a is unblocked (i.e., the a and b signals are "01 ").
Both sensors becomes unblocked (i.e., the a and b signals are "00").

Design a parking lot occupancy counter as follows:

1. Design an FSM with two input signals, a and b, and two output signals, enter and exit .
The enter and exit signals assert one clock cycle when a car enters and one clock
cycle when a car exits the lot, respectively.
2. Derive the Verilog HDL code for the FSM.
3. Design a occupancy counter with two control signals, inc and dec, which increment
and decrement the counter when asserted. Derive the Verilog HDL code.
4. Combine the occupancy counter and the FSM and LED multiplexing circuit. Use two
debounced pushbuttons to mimic operation of the two sensor outputs.

Verify operation of the occupancy counter (in the Labs/TA office hours).

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