Memory and I/O Subsystem: Reference: Introduction To Digital System by Ercegovac, Lang & Moreno, Wiley Publisher
Memory and I/O Subsystem: Reference: Introduction To Digital System by Ercegovac, Lang & Moreno, Wiley Publisher
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Basic components of a computer
• PROCESSOR;
• MEMORY SUBSYSTEM;
• INPUT/OUTPUT (I/O) SUBSYSTEM
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Memory hierarchy
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Specification of a simple processor System
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Memory Subsystem
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Entity Declaration of memory Subsystem
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.comp_pkg.ALL;
ENTITY Memory IS
PORT (Addr : IN MAddrT ; -- memory address bus
Length : IN STD_LOGIC; -- byte/word operand
Rd, Wr : IN STD_LOGIC; -- access control signals
Enable : IN STD_LOGIC; -- enable signal
Rdy : OUT STD_LOGIC; -- access completion signal
Data : INOUT WordT ); -- memory data bus
END Memory;
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I/O subsystem
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Entity Declaration of I/O subsystem
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.comp_pkg.ALL;
ENTITY IO IS
PORT (Addr : IN IOAddrT ; -- I/O address bus
Length : IN STD_LOGIC; -- byte/word control
Rd, Wr : IN STD_LOGIC; -- I/O access control
Enable : IN STD_LOGIC; -- I/O enable control
Rdy : OUT STD_LOGIC; -- I/O completion signal
Data : INOUT WordT ); -- I/O data bus
END IO;
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PROCESSOR
• Processor state
• 32 general-purpose registers (32-bits wide),
called R0, R1, ..., R31;
• a 24-bit Program Counter register (PC);
• a 4-bit Condition Register (CR); and
• a 32-bit Instruction Register (IR).
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Processor State
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Behavior of Processor
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Behavior of Instruction
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INSTRUCTION SEQUENCING
• SEQUENTIAL UNLESS
– 1. UNCONDITIONAL BRANCH
– 2. CONDITIONAL BRANCH
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Instruction Format
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Instruction Set
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Instruction set (cont.)
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Instruction set (cont.)
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