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Generic State Machine

1. Standard finite state machines (FSMs) have a single active state at a time, while multiple active states are used to model pipelines and multiple state machines. 2. Mealy and Moore machines differ in how they assign values to outputs. 3. A generic state machine has one input, one output, and n states. It can be represented using a state chart for easier understanding than a state graph.

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Assini Hussain
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42 views

Generic State Machine

1. Standard finite state machines (FSMs) have a single active state at a time, while multiple active states are used to model pipelines and multiple state machines. 2. Mealy and Moore machines differ in how they assign values to outputs. 3. A generic state machine has one input, one output, and n states. It can be represented using a state chart for easier understanding than a state graph.

Uploaded by

Assini Hussain
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Allowing multiple active states:

Standard FSM is defined for one active state at any given time Multiple active states are used for describing pipeline and multiple state machines

Outputs of Mealy and Moore machines


Difference in assigned values to the outputs

A generic state machine One input, one output and n number states

A general dataflow circuit


Modulo-16 count Uses 8-bit data, a clk and a reset input A 4-bit output called matches If on any two consecutive rising edges of the clk the same data appears on data, output will be incremented by one Hardware required are: register, comparator, counter and few logic gates used as glue logic Data flow without component-level details is shown below:

State machine charts


Alternative to state graph To describe behavior of state machine Also called Algorithmic State Machine (ASM) chart Easier to understand the operation of state machines Basic components of SM chart:

Conditional outputs depends on states and input of the system SM chart is constructed by SM blocks An eg.

Derivation of SM chart
Similar to derivation of state graph Step 1: Draw the block diagram of control unit Step 2: Define the input and output signals to control the network Step 3: Construct SM chart that tests the input signals to generate proper sequence of output signal An eg: SM chart for binary multiplier

VHDL code conversion can be done in a straightforward process CASE statement can be used to specify the states IF statement can be used for conditional boxes

VHDL code

Another eg. DICE Game Workout yourself!!!!!!!

Realization of SM Charts
Similar to state graph realization Consists combinational sub network, together with flip flops Should be in reduced form (reducing redundant states) Before deriving next state, a state assignment must be made

An eg.

Linked State Machines


Large and complex sequential machines can be divided into several smaller machines and linked together referred as linked state machines Similar to dividing larger software programs into smaller procedures

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