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Fifo 1

This document describes a FIFO (First In First Out) module. The FIFO uses a 16-word memory and has ports for data input and output, a clock, write and read enables, and flags to indicate the FIFO status. The FIFO processes data on the rising edge of the clock, writing data to the next memory address when receiving a write enable and reading from the previous address on a read enable. Status flags show if the FIFO is empty, full, or partially full.

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103 views

Fifo 1

This document describes a FIFO (First In First Out) module. The FIFO uses a 16-word memory and has ports for data input and output, a clock, write and read enables, and flags to indicate the FIFO status. The FIFO processes data on the rising edge of the clock, writing data to the next memory address when receiving a write enable and reading from the previous address on a read enable. Status flags show if the FIFO is empty, full, or partially full.

Uploaded by

api-26691029
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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FIFO(First In First Out)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fifo is

Generic(bits : Integer := 8;
words:Integer :=16);
Port ( data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
clk : in std_logic;
wr_en : in std_logic;
read_en : in std_logic;
error : out std_logic;
flag: out std_logic_vector(1 downto 0));
-- flag= "00" -> Empty
-- "11" -> Full
-- "01","10" -> Partial full

end fifo;

architecture Behavioral of fifo is


type vect_array is array(15 downto 0 ) of std_logic_vector(7 downto 0);
signal mem : vect_array;

begin

process(clk,wr_en,read_en)

variable temp1: integer range 0 to 15;

begin
if(clk='1' and clk'event) then
if((wr_en and read_en) = '1') then
error<='1';
elsif(wr_en ='1') then
if(temp1<=15) then
temp1:=temp1+1;
mem(temp1)<= data_in;
end if;
elsif(read_en ='1') then
if(temp1>=1) then
data_out<= mem(temp1);
temp1:=temp1-1;
end if;

end if;
end if;

if(temp1=0) then flag<="00";


elsif(temp1=15) then flag<="11";
else flag<="01";
end if;

end process;

end Behavioral;

RTL Schematic:-

Device utilization summary:-


Selected Device : 2v40cs144-6

Number of Slices: 119 out of 256 46%


Number of Slice Flip Flops: 148 out of 512 28%
Number of 4 input LUTs: 95 out of 512 18%
Number of bonded IOBs: 21 out of 88 23%
Number of GCLKs: 1 out of 16 6%

Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 148 |
-----------------------------------+------------------------+-------+

Timing Summary:-
Speed Grade: -6

Minimum period: 3.281ns (Maximum Frequency: 304.785MHz)


Minimum input arrival time before clock: 3.484ns
Maximum output required time after clock: 5.814ns
Maximum combinational path delay: No path found

Timing Detail:-
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay: 3.281ns (Levels of Logic = 4)
Source: temp1_0 (FF)
Destination: data_out_0 (FF)
Source Clock: clk rising
Destination Clock: clk rising

Data Path: temp1_0 to data_out_0


Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
------------------------------------------------------------------------------ ------------
FDE:C->Q 18 0.449 0.757 temp1_0 (temp1_0)
LUT3_L:I0->LO 1 0.347 0.000 Mmux__n0001_inst_lut3_110
(Mmux__n0001__net1)
MUXF5:I1->O 1 0.345 0.000 Mmux__n0001_inst_mux_f5_0
(Mmux__n0001__net2)
MUXF6:I0->O 1 0.354 0.000 Mmux__n0001_inst_mux_f6_0
(Mmux__n0001__net6)
MUXF7:I0->O 1 0.354 0.383 Mmux__n0001_inst_mux_f7_0 (_n0001<0>)
FDE:D 0.293 data_out_0
-------------------------------------------------------------------------------------------
Total 3.281ns (2.142ns logic, 1.139ns route)
(65.3% logic, 34.7% route)

------------------------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset: 3.484ns (Levels of Logic = 3)
Source: read_en (PAD)
Destination: mem_4_1 (FF)
Destination Clock: clk rising

Data Path: read_en to mem_4_1


Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
----------------------------------------------------------------------- ------------
IBUF:I->O 6 0.653 0.586 read_en_IBUF (read_en_IBUF)
LUT2:I0->O 16 0.347 0.740 Ker30861 (N3088)
LUT4:I3->O 8 0.347 0.621 _n01101 (_n0110)
FDE:CE 0.190 mem_9_0
-----------------------------------------------------------------------------------
Total 3.484ns (1.537ns logic, 1.947ns route)
(44.1% logic, 55.9% route)

--------------------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset: 5.814ns (Levels of Logic = 2)
Source: temp1_0 (FF)
Destination: flag<0> (PAD)
Source Clock: clk rising

Data Path: temp1_0 to flag<0>


Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
----------------------------------------------------------------- ------------
FDE:C->Q 18 0.449 0.756 temp1_0 (temp1_0)
LUT4_D:I3->O 2 0.347 0.518 flag<0>1 (flag_0_OBUF)
OBUF:I->O 3.743 flag_0_OBUF (flag<0>)
------------------------------------------------------------------------------
Total 5.814ns (4.539ns logic, 1.275ns route)
(78.1% logic, 21.9% route)
CPU : 4.29 / 4.74 s | Elapsed : 4.00 / 5.00 s

Total memory usage is 63536 kilobytes.

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